公开(公告)号：US20220230883A1

公开(公告)日：2022-07-21

申请号：US17609194

申请日：2020-05-15

Applicant: The Board of Trustees of the Leland Stanford Junior University ,  The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Dong Ji

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/324 ,  H01L21/266 ,  H01L29/20

Abstract: In certain examples, methods and semiconductor structures are directed to use of a doped buried region (e.g., Mg-dopant) including a III-Nitride material and having a diffusion path (“ion diffusion path”) that includes hydrogen introduced by using ion implantation via at least one ion species. An ion implantation thermal treatment causes hydrogen to diffuse through the ion implanted path and causes activation of the buried region. In more specific examples in which such semiconductor structures have an ohmic contact region at which a source of a transistor interfaces with the buried region, the ohmic contact region is without etching-based damage due at least in part to the post-ion implantation thermal treatment.

公开(公告)号：US20170125574A1

公开(公告)日：2017-05-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US20230031266A1

公开(公告)日：2023-02-02

申请号：US17790675

申请日：2021-01-08

Applicant: The Regents of the University of California ,  The Board of Trustrees of the Leland Stanford Junior University

Inventor： Srabanti Chowdhury ,  Mohamadali Malakoutian ,  Matthew A. Laurent ,  Chenhao Ren ,  Siwei Li

IPC: H01L29/267 ,  H01L21/02 ,  H01L27/06 ,  H01L27/12 ,  H01L27/088

Abstract: In certain examples, methods and semiconductor structures are directed to a method comprising steps of forming by monolithically integrating or seeding via polycrystalline diamond (PCD) particles on a GaN-based layer characterized as including GaN in at least a surface region of the GaN-based layer. After the step of seeding, the PCD particles are grown under a selected pressure to form a diamond layer section and to provide a semi-conductive structure that includes the diamond layer section integrated on or against the surface region of the GaN-based layer.

公开(公告)号：US20220223586A1

公开(公告)日：2022-07-14

申请号：US17571128

申请日：2022-01-07

Applicant: The Board of Trustees of the Leland Stanford Junior University ,  The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Mohamadali Malakoutian ,  Matthew A. Laurent ,  Chenhao Ren ,  Siwei Li

IPC: H01L27/085 ,  H01L21/8258 ,  H01L21/02 ,  H01L23/373 ,  H01L23/00

Abstract: In certain examples, methods and semiconductor structures are directed to an integrated circuit (IC) having a diamond layer section and a GaN-based substrate being monolithically integrated or bonded as part of the same IC. In a specific example, the GaN-based substrate includes GaN, AlxGayN (0

公开(公告)号：US20190115448A1

公开(公告)日：2019-04-18

申请号：US16092154

申请日：2017-05-11

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Dong Ji

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/08 ,  H01L21/02 ,  H01L29/06

Abstract: III-nitride vertical transistors and methods of making the same are disclosed. The transistors can include aperture regions that are formed using ion implantation. The resulting transistors can have improved properties.

公开(公告)号：US20170200833A1

公开(公告)日：2017-07-13

申请号：US14990561

申请日：2016-01-07

Applicant: Lawrence Livermore National Security, LLC ,  The Regents of the University of California

Inventor： Adam Conway ,  Sara Elizabeth Harrison ,  Rebecca J. Nikolic ,  Qinghui Shao ,  Lars Voss ,  Srabanti Chowdhury

IPC: H01L29/808 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L29/8083 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66924 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8122

Abstract: According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

公开(公告)号：US20150137137A1

公开(公告)日：2015-05-21

申请号：US14566443

申请日：2014-12-10

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Srabanti Chowdhury ,  Ramya Yeluri ,  Christophe Hurni ,  Umesh K. Mishra ,  Ilan Ben-Yaacov

IPC: H01L29/778 ,  H01L29/201 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/0646 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66204 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/861

Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

Abstract translation: 具有基于氨（NH3）的分子束外延（MBE）的电流孔径垂直电子晶体管（CAVET）生长的p型氮化镓（p-GaN）作为电流阻挡层（CBL）。 具体来说，CAVET具有用于电流阻塞目的的有源掩埋的镁（Mg）掺杂的GaN层。 这种结构对于大功率开关应用以及需要掩埋有源p-GaN层用于其功能的任何器件是非常有利的。

公开(公告)号：US10903371B2

公开(公告)日：2021-01-26

申请号：US14990561

申请日：2016-01-07

Applicant: Lawrence Livermore National Security, LLC ,  The Regents of the University of California

Inventor： Adam Conway ,  Sara Elizabeth Harrison ,  Rebecca J. Nikolic ,  Qinghui Shao ,  Lars Voss ,  Srabanti Chowdhury

IPC: H01L29/808 ,  H01L29/10 ,  H01L29/20 ,  H01L29/06 ,  H01L29/16 ,  H01L29/812 ,  H01L29/778 ,  H01L29/66 ,  H01L29/04

Abstract: According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

公开(公告)号：US10312361B2

公开(公告)日：2019-06-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L29/51 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US09590088B2

公开(公告)日：2017-03-07

申请号：US14566443

申请日：2014-12-10

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Srabanti Chowdhury ,  Ramya Yeluri ,  Christophe Hurni ,  Umesh K. Mishra ,  Ilan Ben-Yaacov

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/417

CPC classification number: H01L29/7787 ,  H01L29/0646 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66204 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/861

Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

Abstract translation: 具有基于氨（NH3）的分子束外延（MBE）的电流孔径垂直电子晶体管（CAVET）生长的p型氮化镓（p-GaN）作为电流阻挡层（CBL）。 具体来说，CAVET具有用于电流阻塞目的的有源掩埋的镁（Mg）掺杂的GaN层。 这种结构对于大功率开关应用以及需要掩埋有源p-GaN层用于其功能的任何器件是非常有利的。