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公开(公告)号：US4810903A
公开(公告)日：1989-03-07
申请号：US132843
申请日：1987-12-14
IPC分类号： H03K17/567 , H03K19/013 , H03K19/08 , H03K19/0944 , H03K19/02 , H03K17/16 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/0136
摘要： A BICMOS driver circuit is provided having high input impedence and high output current drive with low static power dissipation that provides supply voltages and full logic output voltage swing for circuits having submicron dimensions. An inverter circuit is coupled to a voltage divider circuit and the input terminal for inverting the input signal. A complementary emitter follower circuit is coupled to an output terminal for providing a digital output signal. A current source circuit is coupled to the complementary emitter follower circuit and the input terminal for sourcing current to the complementary emitter follower circuit in response to the input signal. A bipolar bias circuit is coupled to the complementary emitter follower circuit and the inverter circuit for biasing the complementary emitter follower circuit in response to an inverted input signal.
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公开(公告)号：US6127875A
公开(公告)日：2000-10-03
申请号：US130343
申请日：1998-08-13
CPC分类号： H02M3/073
摘要： A voltage boosting circuit which derives an output voltage than is substantially twice the magnitude of a supply voltage applied thereto. The voltage boosting circuit consists of complementary acting boost circuits each having a pair of switches (42A, 52A; 42B, 52B) connected between an input of the voltage boosting circuit, at which is applied the supply voltage, and an output at which the output voltage is produced. Boost capacitors (48A, 48B) are connected between the respective switches of the complementary boost circuits and the switches of the these circuits are opened and closed out of phase with respect to each other in response to clocking signals being applied thereto such that a boosted output voltage is produced during each half cycle of the clocking signals.
摘要翻译： 导出输出电压的升压电路基本上是施加到其上的电源电压的大小的两倍。 升压电路包括互补作用升压电路，每个互补作用升压电路各自具有一对开关（42A，52A; 42B，52B），所述开关连接在施加电源电压的升压电路的输入端和输出端之间， 产生电压。 升压电容器（48A，48B）连接在互补升压电路的相应开关之间，并且这些电路的开关响应于施加到其上的时钟信号相对于彼此而异相地打开和闭合，使得升压输出 在时钟信号的每个半周期产生电压。
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3.发明授权CMOS static ram cell provided with an additional bipolar drive transistor 失效CMOS静态压电池提供一个额外的双极驱动晶体管
公开(公告)号：US4779230A
公开(公告)日：1988-10-18
申请号：US947124
申请日：1986-12-29
CPC分类号： G11C11/41
摘要： A BIMOS memory cell is formed by providing a CMOS static RAM cell with an additional NPN bipolar transistor to provide additional drive current during the read cycle to improve the read time of the memory cell.
摘要翻译： 通过为CMOS静态RAM单元提供附加的NPN双极晶体管来形成BIMOS存储单元，以在读周期期间提供额外的驱动电流，以改善存储单元的读取时间。
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公开(公告)号：US4635087A
公开(公告)日：1987-01-06
申请号：US687530
申请日：1984-12-28
IPC分类号： G11C11/39 , G11C11/411 , H01L27/082 , H01L27/102 , H01L29/74 , G11C11/34 , H01L27/02 , H01L29/72
CPC分类号： H01L27/1025 , G11C11/39 , G11C11/4116 , H01L27/0826
摘要： Bipolar memory arrays having lower quiescent leakage and higher switching speed are constructed by using coupled SCRs formed from vertical PNP and NPN devices. Buried collectors for the PNP and NPN devices are provided within the same isolation tub. A P type plug is used to connect the P collector of the PNP to the P base of the NPN in a region where the P base and P collector overlap. A single N epi-region serves as the base of the PNP and the collector of the NPN. The P plug is located within this N epi-region but part of the N epi-region adjacent to or around the P plug is left so that internal connection of the PNP base and NPN collector is not cut off by the P plug. The structure is particularly suited for use in large memory arrays. The method of fabrication is also described.
摘要翻译： 通过使用由垂直PNP和NPN器件形成的耦合SCR构成具有较低静态泄漏和较高开关速度的双极存储器阵列。 PNP和NPN设备的埋藏式收集器提供在同一隔离桶内。 P型插头用于在P基极和P集电极重叠的区域中将PNP的P集电极连接到NPN的P基极。 单个N外延区域用作PNP的基极和NPN的收集器。 P插头位于该N外延区域内，但是与P插头相邻或附近的N外延区域的一部分保留，使得PNP基极和NPN集电极的内部连接不被P插头切断。 该结构特别适用于大型存储器阵列。 还描述了制造方法。
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公开(公告)号：US5440249A
公开(公告)日：1995-08-08
申请号：US237570
申请日：1994-05-03
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K3/356113 , H03K19/00315 , H03K19/018521
摘要： A voltage level translator circuit converts an input signal referenced between first and second operating potentials to an output signal referenced between second and third operating potentials. The input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in the output stage. The input signal is delayed before driving lower cascoded transistors in the output stage. The output stage transistors are cascoded in a similar manner as the level shifting section. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translator circuit. Additional cascoded transistors may be stacked to extend the range of voltage translation. The voltage level translator circuit is applicable to sub-micron technology.
摘要翻译： 电压电平转换器电路将在第一和第二操作电位之间参考的输入信号转换为在第二和第三操作电位之间参考的输出信号。 输入信号通过级联转换晶体管并由串联逆变器锁存，以驱动输出级的上级串联晶体管。 在输出级驱动较低级联的晶体管之前，输入信号被延迟。 输出级晶体管以与电平移位部分类似的方式被级联。 输入信号的逻辑状态确定输出级中的上级联型晶体管或下级联型晶体管是否被激活，以设置电压电平转换器电路的输出信号的逻辑状态。 可以堆叠附加的级联三极管以延长电压转换的范围。 电压转换器电路适用于亚微米技术。
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6.发明授权BICMOS sense circuit for sensing data during a read cycle of a memory 失效BICMOS感测电路，用于在存储器的读取周期期间感测数据
公开(公告)号：US5229967A
公开(公告)日：1993-07-20
申请号：US577375
申请日：1990-09-04
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/062 , G11C11/419
摘要： A bipolar complementary metal oxide semiconductor (BICMOS) sense circuit for sensing data on read data lines during a read cycle of a memory comprises a load portion and a sense amplifier portion. In one form, the load portion couples true and complement read data lines to a first voltage in response to a start of a read cycle. When the true and complement read data lines exceed a predetermined voltage, the sense amplifier is enabled. The load portion becomes inactive when the voltage on the read data lines reaches approximately the first voltage. Then a selected memory cell provides a differential voltage on a bit line pair, which is coupled to the read data lines, indicating the contents of the selected memory cell. The sense amplifier provides a differential current onto a corresponding read global data line pair in response to the differential voltage. At the termination of the read cycle, the load portion becomes active again and couples the read data lines to a second voltage to disable the sense amplifier. The predetermined voltage is between the first voltage and the second voltage. The circuit increases the speed of the sensing function over a CMOS design, while keeping power consumption to a minimum. In another form, the sense circuit generates a read sense voltage that is substantially independent of non-tracking process variations between P-channel and N-channel field-effect transistors.
摘要翻译： 用于在存储器的读取周期期间读取数据线上的数据的双极互补金属氧化物半导体（BICMOS）感测电路包括负载部分和读出放大器部分。 在一种形式中，负载部分响应于读周期的开始将真数和补码读数据线耦合到第一电压。 当真实和补码读取数据线超过预定电压时，读出放大器使能。 当读取数据线上的电压达到大约第一电压时，负载部分变为无效。 然后，选择的存储单元在位线对上提供差分电压，位线对耦合到读取数据线，指示所选存储单元的内容。 读出放大器响应于差分电压而将差分电流提供给对应的读取全局数据线对。 在读周期结束时，负载部分再次变为有效，并将读数据线耦合到第二电压以禁用读出放大器。 预定电压在第一电压和第二电压之间。 该电路在CMOS设计中增加了感测功能的速度，同时将功耗降至最低。 在另一种形式中，感测电路产生读取感测电压，其基本上与P沟道和N沟道场效应晶体管之间的非跟踪处理变化无关。
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公开(公告)号：US5084665A
公开(公告)日：1992-01-28
申请号：US533199
申请日：1990-06-04
IPC分类号： G05F3/26
CPC分类号： G05F3/267 , Y10S323/901 , Y10S323/907
摘要： A BiMOS voltage reference circuit which includes a bandgap circuit for providing a predetermined voltage at an output of the circuit that is independent of temperature. A start-up and bias circuit coupled to the bandgap circuit for providing a start-up current to the bandgap circuit during power-up and for providing a bias current to the bandgap circuit after power-up. A feedback circuit coupled to the bandgap circuit for maintaining the bias current to the bandgap circuit independent of power supply variations wherein the predetermined voltage at the output of the circuit is also independent of power supply variations as well as temperature.
摘要翻译： 一种BiMOS电压参考电路，其包括用于在独立于温度的电路的输出处提供预定电压的带隙电路。 耦合到带隙电路的启动和偏置电路，用于在上电期间向带隙电路提供启动电流，并且在上电后向带隙电路提供偏置电流。 耦合到带隙电路的反馈电路，用于将偏置电流保持到带隙电路，而与电源变化无关，其中电路输出处的预定电压也与电源变化以及温度无关。
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公开(公告)号：US4785259A
公开(公告)日：1988-11-15
申请号：US150607
申请日：1988-02-01
IPC分类号： G11C11/419 , G11C7/06 , G11C11/416 , H03K5/24 , H03F3/16 , H03F3/45
CPC分类号： H03K5/2445 , G11C7/062 , H03K5/2454
摘要： A BIMOS amplifier having feedback clamping the amplifier's input to a predetermined voltage, minimizes input signal voltage excursions in the presence of large load capacitances. A pair of differentially coupled NPN transistors in response to first and second inputs drive a pair of emitter follower NPN transistors. First and second MOS transistors responsive to first and second enable signals are coupled between the ouptut from each of the emitters of the emitter follower transistors and the first and second inputs, respectively.
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公开(公告)号：US4649295A
公开(公告)日：1987-03-10
申请号：US818463
申请日：1986-01-13
IPC分类号： H03K19/00 , H03K19/017 , H03K19/0944 , H03K19/01 , H03K19/082 , H03K19/094
CPC分类号： H03K19/01721 , H03K19/0013 , H03K19/09448
摘要： A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled to the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between an input terminal and both the upper transistor and the first MOS transistor circuit for providing a high impedance at the input and for biasing both the upper transistor and the first MOS transistor circuit, wherein the first circuit is biased with a larger voltage than the upper transistor for improving the switching speed of the output signal.
摘要翻译： 提供了一种BIMOS电路，其中输出端耦合在上和下NPN推挽晶体管之间，用于提供高电流驱动能力以及没有直流电压。 功耗。 第一MOS晶体管电路耦合到下晶体管以偏置下晶体管。 第二MOS晶体管电路耦合在输入端与上晶体管和第一MOS晶体管电路之间，用于在输入处提供高阻抗并且用于偏置上晶体管和第一MOS晶体管电路，其中第一电路偏置 具有比上部晶体管更大的电压以提高输出信号的开关速度。
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公开(公告)号：US4948991A
公开(公告)日：1990-08-14
申请号：US266613
申请日：1988-11-03
IPC分类号： H03K19/01 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K19/0136
摘要： An ECL transient driver discharges a capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load. A pull-up transistor is coupled to an output terminal for selectively supplying a voltage thereto in response to a first signal from a logic circuit. A pull-down transistor is coupled to the output terminal for selectively sinking a current therefrom in response to a second signal. A comparator circuit is coupled to the pull-down transistor, the logic circuit, and the output terminal, for selectively providing the second signal in response to the first signal and an output voltage on the output terminal.
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