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公开(公告)号：US4810903A
公开(公告)日：1989-03-07
申请号：US132843
申请日：1987-12-14
IPC分类号： H03K17/567 , H03K19/013 , H03K19/08 , H03K19/0944 , H03K19/02 , H03K17/16 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/0136
摘要： A BICMOS driver circuit is provided having high input impedence and high output current drive with low static power dissipation that provides supply voltages and full logic output voltage swing for circuits having submicron dimensions. An inverter circuit is coupled to a voltage divider circuit and the input terminal for inverting the input signal. A complementary emitter follower circuit is coupled to an output terminal for providing a digital output signal. A current source circuit is coupled to the complementary emitter follower circuit and the input terminal for sourcing current to the complementary emitter follower circuit in response to the input signal. A bipolar bias circuit is coupled to the complementary emitter follower circuit and the inverter circuit for biasing the complementary emitter follower circuit in response to an inverted input signal.
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公开(公告)号：US06747494B2
公开(公告)日：2004-06-08
申请号：US10077467
申请日：2002-02-15
IPC分类号： H03L706
CPC分类号： H03L7/0895
摘要： A charge pump arrangement for a phase-locked-loop has a current source circuit (60) which provides charging current to the phase locked loop, and a current sink circuit (90) which depletes charging current from the phase locked loop. The current source circuit (60) and the current sink circuit (90) have slew rates which have a predetermined relationship. In this way, the charge pump causes substantially no non-linear charge injection in the phase-locked-loop. Cascoded current mirrors (75, 85) are utilised to provide a high voltage with thin gate oxide technology. The arrangement has a relatively small die size. Since bias currents of the arrangement are mirrored according to the output current required, improved transient times are produced, leading to reduced phase noise.
摘要翻译： 用于锁相环的电荷泵装置具有向锁相环提供充电电流的电流源电路（60）和从锁相环消耗充电电流的电流吸收电路（90）。 电流源电路（60）和电流吸收电路（90）具有预定关系的转换速率。 以这种方式，电荷泵在锁相环中基本上不引起非线性电荷注入。 Cascoded电流镜（75,85）用于提供具有薄栅极氧化物技术的高电压。 该布置具有相对较小的管芯尺寸。 由于该装置的偏置电流根据所需的输出电流进行镜像，因此产生改善的瞬态时间，导致相位噪声的降低。
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3.发明授权Bipolar memory cell array biasing technique with forward active PNP load cell 失效双向存储单元阵列偏置技术与正向有源PNP称重传感器
公开(公告)号：US5117391A
公开(公告)日：1992-05-26
申请号：US533220
申请日：1990-06-04
申请人： Bor-Yuan Hwang , Thomas P. Bushey
发明人： Bor-Yuan Hwang , Thomas P. Bushey
IPC分类号： G11C11/411 , G11C11/415
CPC分类号： G11C11/4113 , G11C11/415
摘要： A bipolar memory array arranged in a row and column matrix is responsive to a plurality of word line driver transistors for selecting one row of memory cells thereof. The current flowing through each memory cell is provided by a pair or lateral PNP transistor current source loads. The collectors of the word line driver transistors are commonly connected for distributing the source of collector current flowing therethrough between the bases of all of the laterla PNP transistor current sources of the entire memory array which maintains a constant current flow through each of the memory cells during the select and deselect cycles thereby maintaining a constant memory cell array power dissipation which allows for expanded capacity of the memory array and a performance improvement.
摘要翻译： 布置成行和列矩阵的双极存储器阵列响应于用于选择其一行存储器单元的多个字线驱动器晶体管。 流过每个存储单元的电流由一对或横向PNP晶体管电流源负载提供。 字线驱动器晶体管的集电极通常被连接用于在整个存储器阵列的所有后置PNP晶体管电流源的基极之间分配流过其的集电极电流源，其保持恒定的电流流过每个存储器单元 选择和取消选择周期，从而保持恒定的存储单元阵列功率耗散，这允许存储器阵列的扩展容量和性能改进。
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公开(公告)号：US4857479A
公开(公告)日：1989-08-15
申请号：US191923
申请日：1988-05-09
IPC分类号： H01L21/285 , H01L29/417 , H01L29/423 , H01L29/732
CPC分类号： H01L29/7325 , H01L21/28531 , H01L29/41708 , H01L29/42304
摘要： Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lowest poly layer. The lateral epi-poly sidewall contacts are recessed under the intervening oxide layers to separate them from the active device regions in the center of the epi pillar.The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. The exposed edges of the poly layers are oxidized. These edge oxide regions are removed in the holes where the device pillars are epitaxially grown. The remaining edge oxide regions isolate the buried conductor layers, contacts, and isolation walls. The polycrystalline pillar extending from the lowest poly layer to the device surface is formed at the same time as the epi-pillar. The structure is self-aligned and self-registering.
摘要翻译： 具有最小寄生结面积的改进的半导体器件通过使用多个掩埋多晶体导体层形成以与一个或多个柱状外延单晶器件区域进行横向接触而形成。 横向多晶硅触点彼此隔离并且与基板隔离，并且具有至少一个多晶柱延伸到装置的上表面以允许外部连接到最低的多晶硅层。 横向外延层侧壁接触凹陷在中间氧化物层之下，以将它们与外延柱中心的有源器件区分离。 该结构通过沉积三个介电层而形成，其中两个多层夹在其间。 孔被各向异性地蚀刻到最低的多层和基底。 多层的暴露边缘被氧化。 这些边缘氧化物区域在设备柱外延生长的孔中被去除。 剩余的边缘氧化物区域隔离埋入的导体层，接触部和隔离壁。 在与外延柱同时形成从最下面的多层延伸到器件表面的多晶柱。 结构是自我调节和自我登记。
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公开(公告)号：US6026003A
公开(公告)日：2000-02-15
申请号：US215932
申请日：1998-12-18
CPC分类号： H02M3/073 , H02M2003/078
摘要： A charge pump (102) and method of charge pumping a low voltage (V.sub.DD)) to generate a higher voltage (V.sub.PP). A primary pump (160, 179, 180) receives complementary clock signals (CLK1, CLK2) that control charging and transfer cycles of the charge pump. During the charging cycle, a capacitor (150) stores a charge developed from the low voltage. On the transfer cycle, the charge is transferred to an output (138, 177, 178) through a switching transistor (152) disposed in a well region (202) to develop the higher voltage. A secondary pump (162, 187, 188) charge pumps the output voltage to generate a more positive bias voltage for biasing the well region to disable a parasitic PNP transistor of the switching transistor.
摘要翻译： 电荷泵（102）和电荷泵浦低电压（VDD）的方法）以产生较高电压（VPP）。 主泵（160,179,180）接收控制电荷泵的充电和传送周期的互补时钟信号（CLK1，CLK2）。 在充电循环期间，电容器（150）存储从低电压产生的电荷。 在传送周期中，通过布置在阱区（202）中的开关晶体管（152）将电荷转移到输出端（138,177,178）以产生较高的电压。 二次泵（162,187,188）对输出电压进行泵浦以产生更正的偏置电压，以偏置阱区以禁用开关晶体管的寄生PNP晶体管。
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公开(公告)号：US4696097A
公开(公告)日：1987-09-29
申请号：US785414
申请日：1985-10-08
IPC分类号： H01L27/04 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/331 , H01L21/762 , H01L21/768 , H01L21/822 , H01L23/522 , H01L29/43 , H01L29/73 , H01L29/732 , H01L29/74 , H01L29/80 , H01L29/86 , H01L21/283 , H01L21/302
CPC分类号： H01L21/28531 , H01L21/762 , Y10S148/011 , Y10S148/05 , Y10S148/164
摘要： Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lower poly layer.The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. A conformal oxide is applied over the whole structure and anisotropically etched to remove the bottom portions in the hole where the poly pillar and the isolation wall are to be formed and isotropically where the single crystal pillar is to be formed. The remaining oxide regions isolate the buried conductor layers, contacts, and isolation walls. The polycrystalline pillar extending from the lowest poly layer to the device surface is formed at the same time as the epi-pillar. The structure may be made self-aligned and self-registering.
摘要翻译： 具有最小寄生结面积的改进的半导体器件通过使用多个掩埋多晶体导体层形成以与一个或多个柱状外延单晶器件区域进行横向接触而形成。 横向聚触点彼此隔离并且与基板隔离，并且具有至少一个延伸到该设备的上表面的多晶柱，以允许外部连接到下多层。 该结构通过沉积三个介电层而形成，其中两个多层夹在其间。 孔被各向异性地蚀刻到最低的多层和基底。 在整个结构上施加保形氧化物并进行各向异性蚀刻以去除要在其中形成多晶柱和形成隔离壁的孔中的底部，并且在各向同性地形成单晶柱。 剩余的氧化物区域隔离埋入的导体层，接触部和隔离壁。 在与外延柱同时形成从最下面的多层延伸到器件表面的多晶柱。 该结构可以进行自对准和自我登记。
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公开(公告)号：US5898617A
公开(公告)日：1999-04-27
申请号：US859962
申请日：1997-05-21
CPC分类号： G11C16/28
摘要： A circuit (28) and method of sensing data stored in a memory circuit provide a reference current (I.sub.REF) that tracks memory cell current (I.sub.BIT) over a range of temperatures and power supply voltages. A comparator circuit (66) senses the memory cell current with respect to the reference current to produce the stored data (V.sub.DATA) By sensing current rather than voltage, the voltage swing on a high capacitance bitline (39) can be reduced to improve speed. The reference current is set during testing of the circuit by applying programming voltages (V.sub.WELL, V.sub.CG, V.sub.BL) to a reference device (52) that matches a storage device (36) in the memory cell (30).
摘要翻译： 检测存储在存储器电路中的数据的电路（28）和方法提供在温度范围和电源电压上跟踪存储单元电流（IBIT）的参考电流（IREF）。 比较器电路（66）相对于参考电流感测存储单元电流以产生存储的数据（VDATA）通过感测电流而不是电压，可以减小高电容位线（39）上的电压摆幅以提高速度。 通过将编程电压（VWELL，VCG，VBL）应用于与存储单元（30）中的存储装置（36）匹配的参考装置（52），在电路测试期间设置参考电流。
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公开(公告)号：US5828607A
公开(公告)日：1998-10-27
申请号：US861078
申请日：1997-05-21
摘要： A circuit and method modify data stored in a storage element (30) of a memory circuit (110) when high voltages used for such modification exceed transistor breakdowns. A charge pump (302) produces a pumped voltage (V.sub.P1) for modifying the data. A monitor circuit (304) produces an enable signal (V.sub.PEN) to activate other power supply voltages when the pumped voltage reaches a predetermined voltage level for allowing the data to be modified. A routing circuit (832) selects between the pumped voltage and a first voltage (V.sub.DD) in response to a first control signal (HVENABLEP) to produce a selected voltage. A switching circuit (802-808) passes the selected voltage to the storage element (30) to modify the data when the first supply voltage is selected by the routing circuit.
摘要翻译： 当用于这种修改的高电压超过晶体管故障时，电路和方法修改存储在存储电路（110）的存储元件（30）中的数据。 电荷泵（302）产生用于修改数据的泵浦电压（VP1）。 当泵浦电压达到预定电压电平以允许数据被修改时，监视器电路（304）产生使能信号（VPEN）以激活其它电源电压。 路由电路（832）响应于第一控制信号（HVENABLEP）在泵浦电压和第一电压（VDD）之间选择以产生所选择的电压。 当由路由电路选择第一电源电压时，开关电路（802-808）将所选择的电压传递到存储元件（30）以修改数据。
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公开(公告)号：US4871928A
公开(公告)日：1989-10-03
申请号：US235128
申请日：1988-08-23
申请人： Thomas P. Bushey
发明人： Thomas P. Bushey
IPC分类号： H03K5/151 , H03K19/013 , H03K19/0175 , H03K19/0944
CPC分类号： H03K5/151 , H03K19/0136 , H03K19/017518 , H03K19/09448
摘要： A BICMOS inverter circuit having a high input impedance, improved switching characteristics, low power requirements, high noise immunity, high drive capability, an increased output voltage swing, reduced body effect, high current drivability and improved power dissipation comprises a CMOS inverter for receiving an input signal and bipolar push-pull output transistors for supplying an output. An intermediate CMOS stage is coupled between the CMOS inverter and the bipolar push-pull output transistors and to power supply voltages in a manner that eliminates body effect.
摘要翻译： 具有高输入阻抗，改善的开关特性，低功率要求，高抗扰度，高驱动能力，增加的输出电压摆幅，减小的体效应，高电流驱动能力和改善的功耗的BICMOS逆变器电路包括用于接收 输入信号和用于提供输出的双极推挽输出晶体管。 中间CMOS级耦合在CMOS反相器和双极推挽输出晶体管之间，并以消除身体效应的方式耦合到电源电压。
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公开(公告)号：US4806796A
公开(公告)日：1989-02-21
申请号：US174269
申请日：1988-03-28
申请人： Thomas P. Bushey , Bor-Yuan Hwang
发明人： Thomas P. Bushey , Bor-Yuan Hwang
IPC分类号： H03K19/013 , H03K19/086
CPC分类号： H03K19/013 , H03K19/086
摘要： An active load for a CML or ECL logic gate for substantially increasing the speed of the gate comprises a transistor having its base coupled to its collector by a first resistor, and its collector-emitter path coupled in series with a second resistor. This load provides an inductive impedance when the small signal emitter resistance is less than the sum of the resistance of the base and the first resistor, causing a peaking effect resulting in high switching speed.
摘要翻译： 用于实质上增加栅极速度的CML或ECL逻辑门的有源负载包括晶体管，其基极通过第一电阻耦合到其集电极，并且其集电极 - 发射极路径与第二电阻器串联耦合。 当小信号发射极电阻小于基极和第一电阻器的电阻之和时，此负载提供电感阻抗，导致峰值效应导致高开关速度。
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