公开(公告)号：US20090057755A1

公开(公告)日：2009-03-05

申请号：US11845448

申请日：2007-08-27

申请人： Thomas W. Dyer ,  Oh-Jung Kwon ,  Nivo Rovedo ,  O Sung Kwon ,  Bong-Seok Suh

发明人： Thomas W. Dyer ,  Oh-Jung Kwon ,  Nivo Rovedo ,  O Sung Kwon ,  Bong-Seok Suh

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.

摘要翻译： 本文公开了一种半导体器件，其包括形成在半导体衬底的表面上的栅极叠层; 形成在栅堆叠的每个垂直侧壁上的垂直氮化物隔离元件; 垂直氮化物间隔物的覆盖半导体衬底的部分; 形成在所述半导体衬底上的与所述栅叠层相邻的硅化物接触，所述硅化物接触与形成在所述半导体衬底中的漏极和源极区域可操作地连通; 以及设置在所述垂直氮化物间隔元件和所述硅化物接触之间的氧化物间隔物; 该氧化物间隔件用于在蚀刻过程期间最小化邻近垂直氮化物间隔物的底切。

公开(公告)号：US20080169535A1

公开(公告)日：2008-07-17

申请号：US11622588

申请日：2007-01-12

申请人： Shahid A. Butt ,  Thomas W. Dyer ,  Oh-Jung Kwon ,  Jack A. Mandelman ,  Haining S. Yang

发明人： Shahid A. Butt ,  Thomas W. Dyer ,  Oh-Jung Kwon ,  Jack A. Mandelman ,  Haining S. Yang

IPC分类号： H01L29/06 ,  H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/28123 ,  H01L21/3088 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/78

摘要： The present invention provides structures and methods for providing multiple parallel V-shaped faceted grooves with sub-lithographic widths on a semiconductor substrate for enhanced performance MOSFETs. A self-aligning self-assembling material is used to pattern multiple parallel sub-lithographic lines. By employing an anisotropic etch that produces crystallographic facets on a semiconductor surface, multiple adjoining parallel V-shaped grooves with sub-lithographic groove widths are formed. While providing enhanced mobility for the MOSFET, the width of the MOSFET is not limited by the depth of focus in subsequent lithographic steps or the thickness of semiconductor layer above a BOX layer due to the sub-lithographic widths of the V-shaped grooves and the consequent reduction in the variation of the vertical profile. Also, the MOSFET has a well defined threshold voltage due to the narrow widths of each facet.

摘要翻译： 本发明提供了用于在半导体衬底上提供具有亚光刻宽度的多个平行V形刻面槽以提高性能MOSFET的结构和方法。 使用自对准自组装材料来对多个平行的次平版印刷线进行图案化。 通过采用在半导体表面上产生结晶小面的各向异性蚀刻，形成具有亚光刻槽宽度的多个相邻的平行V形槽。 在为MOSFET提供增强的移动性的同时，MOSFET的宽度不受后续光刻步骤中的深度深度或BOX层上方的半导体层厚度的限制，这是由于V形沟槽的次平版印刷宽度和 从而导致垂直剖面变化的减小。 此外，由于每个刻面的窄宽度，MOSFET具有明确的阈值电压。

公开(公告)号：US20110156110A1

公开(公告)日：2011-06-30

申请号：US13043059

申请日：2011-03-08

申请人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

发明人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

IPC分类号： H01L29/772

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

摘要翻译： 形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。 当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。 然后从栅电极的侧壁去除牺牲隔离物。 然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管） 。

公开(公告)号：US07923365B2

公开(公告)日：2011-04-12

申请号：US11874118

申请日：2007-10-17

申请人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

发明人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

摘要翻译： 形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。 当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。 然后从栅电极的侧壁去除牺牲隔离物。 然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管） 。

公开(公告)号：US20090101979A1

公开(公告)日：2009-04-23

申请号：US11874118

申请日：2007-10-17

申请人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

发明人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

摘要翻译： 形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。 当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。 然后从栅电极的侧壁去除牺牲隔离物。 然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管） 。

公开(公告)号：US20130001660A1

公开(公告)日：2013-01-03

申请号：US13615955

申请日：2012-09-14

申请人： Thomas W. Dyer

发明人： Thomas W. Dyer

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7848

摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

公开(公告)号：US08063449B2

公开(公告)日：2011-11-22

申请号：US12626496

申请日：2009-11-25

申请人： Jin-Ping Han ,  Thomas W. Dyer ,  Henry Utomo ,  Rajendran Krishnasamy

发明人： Jin-Ping Han ,  Thomas W. Dyer ,  Henry Utomo ,  Rajendran Krishnasamy

IPC分类号： H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.

摘要翻译： 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。 移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。 在衬套上形成填充材料。 填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

公开(公告)号：US07989357B2

公开(公告)日：2011-08-02

申请号：US11950741

申请日：2007-12-05

申请人： Thomas W. Dyer ,  James J. Toomey

发明人： Thomas W. Dyer ,  James J. Toomey

IPC分类号： H01L23/48

CPC分类号： H01L21/8258 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/31144

摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.

摘要翻译： 公开了图案化半导体结构的方法。 该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。 在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。 通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。 使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。 复合材料层包括在层内由直边限定的离散块中的不同材料。

公开(公告)号：US07964910B2

公开(公告)日：2011-06-21

申请号：US11873731

申请日：2007-10-17

申请人： Thomas W. Dyer

发明人： Thomas W. Dyer

IPC分类号： H01L29/66

CPC分类号： H01L29/6656 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7848

摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

摘要翻译： 公开了一种结合外延​​沉积的源/漏半导体膜的晶体管和用于形成晶体管的方法。 晶体蚀刻用于在硅衬底中的沟道区和沟槽隔离区之间形成凹陷。 每个凹部具有与沟道区相邻的第一轮廓和具有与沟槽隔离区相邻的第二轮廓的第一侧。 晶体蚀刻确保第二轮廓成角度，使得所有暴露的凹部表面都包含硅。 因此，可以通过外延沉积而不形成凹坑来填充凹部。 可以使用附加的工艺步骤来确保凹部的第一侧形成有增强通道区域中的期望应力的不同轮廓。

公开(公告)号：US07863646B2

公开(公告)日：2011-01-04

申请号：US11956043

申请日：2007-12-13

申请人： Michael P. Belyansky ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

发明人： Michael P. Belyansky ,  Xiangdong Chen ,  Thomas W. Dyer ,  Geng Wang ,  Haining S. Yang

IPC分类号： H01L31/111 ,  H01L21/00

CPC分类号： H01L21/823807 ,  H01L27/092 ,  H01L29/7843

摘要： A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.

摘要翻译： 晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。 第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。 此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。 此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。