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公开(公告)号：US06131255A
公开(公告)日：2000-10-17
申请号：US139452
申请日：1998-08-25
IPC分类号： G01R1/073 , G01R31/28 , H01L21/66 , H01L21/98 , H01L23/32 , H01L23/34 , H01L25/065 , H01L21/68
CPC分类号： H01L25/50 , G01R1/07314 , G01R31/2886 , H01L22/22 , H01L23/32 , H01L23/34 , H01L25/0652 , H01L2924/0002 , Y10T29/41
摘要： An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary die temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.
摘要翻译： 用于集成晶片级半导体集成电路并将其与其他系统接口的装置。 将晶片，部分晶片，管芯或多个相配合到与使用小导电柱电接触每个管芯上的焊盘的印刷电路板（PCB）。 PCB依次连接到其他电子系统。 整个装置结合到利用装置中的骰子的其他系统中。 该装置可以装配有加热元件和冷却通道，以产生用于老化，测试和操作的必要的模具温度。 该装置易于适应于在堆叠配置中包括更多的骰子。
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公开(公告)号：US5200917A
公开(公告)日：1993-04-06
申请号：US800582
申请日：1991-11-27
申请人： James M. Shaffer , Karl H. Mauritz , Glen Atkins
发明人： James M. Shaffer , Karl H. Mauritz , Glen Atkins
摘要： The invention relates to a stacked integrated circuit module 20 which is interchangeable with standard printed circuit boards. Module 20 has two PCBs 22 and 24 and multiple memory ICs 26a-26d mounted on the PCBs. A board alignment support 48 is provided between PCBs 22 and 24 to support the PCBs in a spaced and substantially parallel relation and to provide electrical interfacing between the two PCBs. PCB 22 has an edge connector 44 adapted to be inserted into standard receptacle connectors provided on a mother board. According to this stacked arrangement, memory ICs 26c and 26d are addressable through connector 44, conductive paths formed on PCB 22, board alignment support 48, and conductive paths formed on PCB 24.
摘要翻译： 本发明涉及一种与标准印刷电路板可互换的堆叠集成电路模块20。 模块20具有安装在PCB上的两个PCB 22和24以及多个存储器IC 26a-26d。 PCB对准支撑件48设置在PCB 22和24之间，以便以间隔的和基本平行的关系支撑PCB，并且在两个PCB之间提供电接口。 PCB 22具有适于插入设置在母板上的标准插座连接器中的边缘连接器44。 根据这种堆叠布置，存储器IC 26c和26d可通过连接器44寻址，形成在PCB 22上的导电路径，板对准支架48和形成在PCB24上的导电路径。
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公开(公告)号：US06049977A
公开(公告)日：2000-04-18
申请号：US856991
申请日：1997-05-15
CPC分类号： G01R31/2862 , G01R31/2886 , H05K3/4007 , G01R31/2863 , H05K1/095 , H05K2201/035 , H05K2201/0367 , H05K3/3457 , Y10T29/49149 , Y10T29/49155 , Y10T29/49156
摘要： A method of forming electrically conductive pillars on a printed circuit board by providing a printed circuit board having a plurality of electrical traces and forming a plurality of elongate, electrically conductive pillars of superimposed layers of solder and conductive polymer on the printed circuit board. The elongate, electrically conductive pillars are connected by a first end to the electrical traces of the printed circuit board and extend substantially perpendicularly from the printed circuit board such that a second end of each of the plurality of elongate, electrically conductive pillars lies in substantially a common plane which is substantially perpendicular to and above said printed circuit board.
摘要翻译： 一种在印刷电路板上形成导电柱的方法，该方法是通过提供具有多个电迹线的印刷电路板，并在印刷电路板上形成多个细长导电的叠层焊料和导电聚合物的导电柱。 细长的导电柱通过第一端连接到印刷电路板的电迹线并且从印刷电路板基本上垂直地延伸，使得多个细长导电柱中的每一个的第二端基本上位于 基本上垂直于所述印刷电路板上方的公共平面。
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公开(公告)号：US6163490A
公开(公告)日：2000-12-19
申请号：US401554
申请日：1999-09-22
申请人： James M. Shaffer , Brent Keeth , Eugene H. Cloud , Salman Akram
发明人： James M. Shaffer , Brent Keeth , Eugene H. Cloud , Salman Akram
IPC分类号： G11C7/00
摘要： Defective memory is programmed to have a contiguous address space by dividing the logical address space of the memory into a plurality of address sections. The address section containing the address mapped to a defective memory location is identified. The physical memory locations originally mapped to the addresses in the identified address section are remapped to addresses in an address section at one end of the address space. The addresses in the end address section are disabled. Alternatively, spare memory is provided and the addresses in the end address section are remapped to physical locations in the spare memory. A similar remapping procedure is applied to repair defective data paths in a memory. The remapping procedure is applicable to memory devices or memory modules.
摘要翻译： 通过将存储器的逻辑地址空间划分成多个地址部分，将有缺陷的存储器编程为具有连续的地址空间。 识别包含映射到有缺陷的存储器位置的地址的地址部分。 最初映射到所识别的地址部分中的地址的物理存储器位置被重新映射到地址空间一端的地址段中的地址。 结束地址部分中的地址被禁用。 或者，提供备用存储器，并将结束地址部分中的地址重新映射到备用存储器中的物理位置。 应用类似的重新映射程序来修复存储器中的有缺陷的数据路径。 重映射过程适用于存储器或存储器模块。
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公开(公告)号：US5570032A
公开(公告)日：1996-10-29
申请号：US108097
申请日：1993-08-17
CPC分类号： G01R31/2862 , G01R31/2886 , H05K3/4007 , G01R31/2863 , H05K1/095 , H05K2201/035 , H05K2201/0367 , H05K3/3457 , Y10T29/49149 , Y10T29/49155 , Y10T29/49156
摘要： An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.
摘要翻译： 用于半导体集成电路的晶片刻蚀和测试的装置及其利用方法。 将晶片与使用小导电柱与每个管芯上的焊盘电接触的印刷电路板相配合。 设备内整个晶片的单精确对准允许并行测试晶圆上的所有晶片，无需单独探测每个晶片。 该设备配有加热元件和冷却通道，以产生必要的晶圆温度，用于老化和测试。 利用的方法消除了对老化和测试之外的有缺陷的骰子的处理，从而提高了生产量。
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公开(公告)号：US869758A
公开(公告)日：1907-10-29
申请号：US1906342982
申请日：1906-11-12
申请人： JAMES M SHAFFER
发明人： WARELE ANTONE F
CPC分类号： B60D1/00
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公开(公告)号：US5815427A
公开(公告)日：1998-09-29
申请号：US825871
申请日：1997-04-02
申请人： Eugene H. Cloud , Brent Keeth , Salman Akram , James M. Shaffer , Alex Closson
发明人： Eugene H. Cloud , Brent Keeth , Salman Akram , James M. Shaffer , Alex Closson
CPC分类号： G11C5/06 , H01L24/50 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05554 , H01L2224/48137 , H01L2224/48227 , H01L2224/49109 , H01L2224/49175 , H01L2224/73257 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/06596 , H01L24/06 , H01L24/16 , H01L24/48 , H01L2924/00014 , H01L2924/01033 , H01L2924/01087 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311
摘要： A modular circuit includes a memory module that has an array of memory cells, a communication module that has communication circuitry for coupling signals between the array and external circuitry, and an interconnection module that electrically interconnects the array on the memory module and the communication circuitry on the communication module. The memory and communication modules may also be mounted to the interconnection module. Alternatively, the memory and interface modules may be electrically interconnected and mounted to each other, in which case the interconnection module is not required.
摘要翻译： 模块化电路包括具有存储器单元阵列的存储器模块，具有用于耦合阵列和外部电路之间的信号的通信电路的通信模块以及将存储器模块上的阵列和通信电路电互连的互连模块， 通讯模块。 存储器和通信模块也可以安装到互连模块。 或者，存储器和接口模块可以电互连并彼此安装，在这种情况下，不需要互连模块。
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公开(公告)号：US5276834A
公开(公告)日：1994-01-04
申请号：US621869
申请日：1990-12-04
CPC分类号： G11C29/76 , G06F11/1044
摘要： A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU).
摘要翻译： 一种备用存储器装置，其中存储器阵列中的有缺陷的芯片可以用相同结构的备用芯片电子地替代。 首先通过诸如纠错码（ECC），校验和或奇偶校验的适当手段来检测和定位有缺陷的存储器芯片。 构成了在读取缺陷存储器芯片时利用存储器备用芯片来替换有缺陷的芯片的致动器芯片。 该支持者芯片包括具有用于从中央处理单元（CPU）接收数据并将数据路由到备用存储器芯片的数据的地址寄存器的交叉点存储器（CPM）单元。 交叉点存储器（CPM）单元由来自（CPU）的控制输入启动。
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公开(公告)号：US6081463A
公开(公告)日：2000-06-27
申请号：US30498
申请日：1998-02-25
申请人： James M. Shaffer , Brent Keeth , Eugene H. Cloud , Salman Akram
发明人： James M. Shaffer , Brent Keeth , Eugene H. Cloud , Salman Akram
IPC分类号： G11C7/00
摘要： Defective memory is programmed to have a contiguous address space by dividing the logical address space of the memory into a plurality of address sections. The address section containing the address mapped to a defective memory location is identified. The physical memory locations originally mapped to the addresses in the identified address section are remapped to addresses in an address section at one end of the address space. The addresses in the end address section are disabled. Alternatively, spare memory is provided and the addresses in the end address section are remapped to physical locations in the spare memory. A similar remapping procedure is applied to repair defective data paths in a memory. The remapping procedure is applicable to memory devices or memory modules.
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公开(公告)号：US5831445A
公开(公告)日：1998-11-03
申请号：US661419
申请日：1996-06-07
CPC分类号： G01R31/2862 , G01R31/2886 , H05K3/4007 , G01R31/2863 , H05K1/095 , H05K2201/035 , H05K2201/0367 , H05K3/3457 , Y10T29/49149 , Y10T29/49155 , Y10T29/49156
摘要： An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization is disclosed. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.
摘要翻译： 公开了一种用于半导体集成电路的晶片刻蚀和测试的装置及其应用的方法。 将晶片与使用小导电柱与每个管芯上的焊盘电接触的印刷电路板相配合。 设备内整个晶片的单精确对准允许并行测试晶圆上的所有晶片，无需单独探测每个晶片。 该设备配有加热元件和冷却通道，以产生必要的晶圆温度，用于老化和测试。 利用的方法消除了对老化和测试之外的有缺陷的骰子的处理，从而提高了生产量。
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