公开(公告)号：US09318378B2

公开(公告)日：2016-04-19

申请号：US10923123

申请日：2004-08-21

申请人： Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  David Vigar ,  Liang Choo Hsia ,  Kin Leong Pey

发明人： Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  David Vigar ,  Liang Choo Hsia ,  Kin Leong Pey

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L21/0276 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

公开(公告)号：US07253097B2

公开(公告)日：2007-08-07

申请号：US11160624

申请日：2005-06-30

申请人： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

发明人： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846

摘要： An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

摘要翻译： 集成电路系统包括提供其上设置有半导体器件的半导体衬底。 第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。 在第一导体芯上形成停止层。 在停止层上形成第二电介质层。 在第二电介质层中形成沟道和通孔。 第二介质层中的通道和通孔被湿清洗。 沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。 从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

公开(公告)号：US20070001303A1

公开(公告)日：2007-01-04

申请号：US11160624

申请日：2005-06-30

申请人： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

发明人： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

IPC分类号： H01L23/52

CPC分类号： H01L21/76831 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846

摘要： An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

摘要翻译： 集成电路系统包括提供其上设置有半导体器件的半导体衬底。 第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。 在第一导体芯上形成停止层。 在停止层上形成第二电介质层。 在第二电介质层中形成沟道和通孔。 第二介质层中的通道和通孔被湿清洗。 沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。 从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

公开(公告)号：US06890854B2

公开(公告)日：2005-05-10

申请号：US09726903

申请日：2000-11-29

申请人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

发明人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L21/26

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

摘要翻译： 公开了一种用于进行镍盐化的方法和装置。 镍硅化物工艺通常包括：形成包括部分制造的集成电路部件和硅衬底的处理衬底; 将氮气掺入经处理的基底中; 将镍沉积在经处理的基底上; 对经处理的基板退火以形成单一硅化镍; 去除未反应的镍; 并执行串联程序来完成集成电路制造。 该镍硅化物工艺增加了退火温度范围，通过盐化可在硅上形成连续的薄镍单硅化物层。 它还延迟了单一硅化镍薄膜的聚集开始到更高的退火温度。 此外，该镍硅化物工艺延迟了从单一硅化镍到更高电阻率的二硅化镍的转变到更高的退火温度。 它还减少了镍增强的多晶硅晶粒生长，以防止层反转。 这种镍硅化物工艺的一些实施例可以用于另外标准的自对准硅化物工艺中，以形成具有低电阻率晶体管栅电极和源极/漏极接触的集成电路器件。

公开(公告)号：US06391731B1

公开(公告)日：2002-05-21

申请号：US09784251

申请日：2001-02-15

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/6659

摘要： A new method of forming MOS transistors with shallow source and drain extensions and deep source and drain junctions in the manufacture of an integrated circuit device has been achieved. Gates are provided overlying a semiconductor substrate. Temporary sidewall spacers are formed on the gates. Ions are implanted into the exposed semiconductor substrate to form a deep amorphous layer. Ions are implanted into the deep amorphous layer to form pre-annealed source and drain junctions. The temporary sidewall spacers are removed. Ions are implanted into the exposed semiconductor substrate to form a shallow amorphous layer. Ions are implanted into the shallow amorphous layer to form pre-annealed source and drain extensions. A capping layer may be deposited overlying the semiconductor substrate and the gates to protect the semiconductor substrate during irradiation. The semiconductor substrate is irradiated with laser light to melt the amorphous layer while the crystalline regions of the semiconductor substrate remain in solid state. Ions in the pre-annealed source and drain junctions diffuse in the deep amorphous layer while ions in the pre-annealed source and drain extensions diffuse into the shallower amorphous layer. The source and drain junctions and the source and drain extensions for the transistors are thereby simultaneously formed.

摘要翻译： 已经实现了在集成电路器件的制造中形成具有浅源极和漏极延伸以及深源极和漏极结的MOS晶体管的新方法。 盖板覆盖半导体衬底。 在门上形成临时侧墙。 将离子注入到暴露的半导体衬底中以形成深非晶层。 将离子注入到深非晶层中以形成预退火的源极和漏极结。 移除临时侧壁间隔物。 将离子注入到暴露的半导体衬底中以形成浅的非晶层。 将离子注入到浅非晶层中以形成预退火的源极和漏极延伸。 覆盖半导体衬底和栅极的覆盖层可以沉积，以在照射期间保护半导体衬底。 半导体衬底用激光照射以熔化非晶层，同时半导体衬底的结晶区保持固态。 预退火源极和漏极结中的离子在深非晶层中扩散，而预退火的源极和漏极延伸部中的离子扩散到较浅的非晶层中。 从而同时形成晶体管的源极和漏极结以及源极和漏极延伸。

公开(公告)号：US06365446B1

公开(公告)日：2002-04-02

申请号：US09609751

申请日：2000-07-03

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

摘要翻译： 一种用于制造具有深源极/漏极结的MOS型晶体管和具有期望的界面和电学性质的薄的硅化物触点的方法。 这些器件通过一种方法产生，该方法涉及通过离子注入，栅极，源极和漏极区域的非晶化，金属层的形成，通过金属层的离子注入，形成覆盖层和随后的激光退火 。

公开(公告)号：US06335253B1

公开(公告)日：2002-01-01

申请号：US09614557

申请日：2000-07-12

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See ,  Andrew Thye Shen Wee

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See ,  Andrew Thye Shen Wee

IPC分类号： H01L21336

CPC分类号： H01L21/268 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659

摘要： A new method of forming MOS transistors with shallow source and drain extensions and self-aligned silicide in the has been achieved. Gates are provided overlying a semiconductor substrate. Temporary sidewall spacers are formed on the gates. Ions are implanted into the semiconductor substrate and the polysilicon layer to form deep amorphous layers beside the spacers and shallow amorphous layers under the spacers. The spacers are removed. Ions are implanted to form lightly doped junctions in the shallower amorphous layer. Permanent sidewall spacers are formed on the gates. Ions are implanted to form heavily doped junctions in the deeper amorphous layer. A metal layer is deposited. A capping layer is deposited to protect the metal layer during irradiation. The integrated circuit device is irradiated with laser light to melt the amorphous layer while the crystalline polysilicon and semiconductor substrate remain in solid state. The metal layer is heated, and may be melted, to cause reaction with the silicon to form silicide. Ions in the heavily doped junctions and in the lightly doped junctions are also thereby diffused into the amorphous layer. The deep source and drain junctions, the shallow source and drain extensions, and a silicide layer are simultaneously formed. A heat treatment crystallizes the silicide to improve resistivity.

摘要翻译： 已经实现了一种形成具有浅源极和漏极延伸和自对准硅化物的MOS晶体管的新方法。 盖板覆盖半导体衬底。 在门上形成临时侧墙。 将离子注入到半导体衬底和多晶硅层中，以在间隔物旁边的隔离层和浅非晶层之间形成深非晶层。 去除间隔物。 在较浅的非晶层中植入离子以形成轻掺杂的结。 在门上形成永久侧壁间隔物。 植入离子以在较深的非晶层中形成重掺杂的结。 沉积金属层。 沉积覆盖层以在照射期间保护金属层。 用激光照射集成电路器件以熔化非晶层，同时晶体多晶硅和半导体衬底保持固态。 金属层被加热并且可能被熔化，从而与硅反应形成硅化物。 在重掺杂结和轻掺杂结中的离子也因此扩散到非晶层中。 同时形成深源极和漏极结，浅源极和漏极延伸部分以及硅化物层。 热处理使硅化物结晶以提高电阻率。

公开(公告)号：US06624489B2

公开(公告)日：2003-09-23

申请号：US10033284

申请日：2001-12-31

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L2976

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

公开(公告)号：US07030451B2

公开(公告)日：2006-04-18

申请号：US11081908

申请日：2005-03-15

申请人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

发明人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L29/78

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US07892905B2

公开(公告)日：2011-02-22

申请号：US11195196

申请日：2005-08-02

申请人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

IPC分类号： H01L31/0216 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  Y10S438/938

摘要： A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

摘要翻译： 已经开发了通过形成相邻的硅 - 锗源/漏区来形成用于MOSFET器件的应变沟道区的工艺。 该方法的特征在于硅 - 锗层的覆盖沉积，或硅 - 锗层在源极/漏极延伸区域的暴露部分上的选择性生长。 激光退火程序通过消耗硅 - 锗层的底部部分和下面的源极/漏极区域的顶部部分而导致硅 - 锗源极/漏极区域的形成。 通过经由激光退火形成硅 - 锗源/漏区的优化可以通过在沉积硅 - 锗层之前施加到源/漏区的暴露部分的预非晶化注入（PAI）程序来实现。 在激光退火过程之后，硅 - 锗层的未反应顶部被选择性地去除。