公开(公告)号：US5345316A

公开(公告)日：1994-09-06

申请号：US978083

申请日：1992-11-17

申请人： Tohru Ozaki ,  Hitoshi Horie ,  Hideyuki Shirai

发明人： Tohru Ozaki ,  Hitoshi Horie ,  Hideyuki Shirai

IPC分类号： H04N1/413 ,  G06T9/00 ,  H04N1/411 ,  H04N1/417 ,  H04N1/419 ,  H04N1/41 ,  H04N1/40

CPC分类号： H04N1/4175 ,  H04N1/411

摘要： An image data encoding/decoding apparatus having an encoder and decoder for processing image data such as facsimile data, in which two different streams of image data can be encoded concurrently by using a single encoding circuit section, and two different streams of encoded data can be decoded concurrently using a single decoding section. The encoded data obtained for each scan line portion of the image data are modified, if necessary, to be converted to an integral number of fixed-size amounts of data such as bytes, for subsequent storage in memory. During decoding processing, the encoded data line portions are restored to their respective original forms prior to decoding processing, by controlled operation of registers in which the encoded data are temporarily written in and then serially read out.

摘要翻译： 具有用于处理诸如传真数据的图像数据的编码器和解码器的图像数据编码/解码装置可以通过使用单个编码电路部分同时编码两个不同的图像数据流，以及两个不同的编码数据流可以是 使用单个解码部分同时解码。 如果需要，对图像数据的每个扫描线部分获得的编码数据进行修改，以将其转换成固定大小的诸如字节的数据量的整数，以便随后存储在存储器中。 在解码处理期间，编码数据线部分在解码处理之前通过被编码数据被暂时写入然后被串行读出的寄存器的受控操作被恢复到它们各自的原始形式。

公开(公告)号：US5331425A

公开(公告)日：1994-07-19

申请号：US818572

申请日：1992-01-09

申请人： Tohru Ozaki ,  Hitoshi Horie ,  Hideyuki Shirai

发明人： Tohru Ozaki ,  Hitoshi Horie ,  Hideyuki Shirai

IPC分类号： G06T9/00 ,  H04N1/413 ,  H04N1/41

CPC分类号： H04N1/413

摘要： A data encoding apparatus, applicable for example to a facsimile apparatus, increases the degree of image data compression that can be achieved by a variable length encoding scheme, by limiting the maximum amount of data outputted from the encoding apparatus for each scan line to the amount of unencoded image data in a scan line. Generation of increased amounts of data in the case of certain types of image content, as a result of the variable length encoding, is thereby eliminated with a consequent increase in encoding efficiency.

摘要翻译： 可应用于传真装置的数据编码装置通过将从每个扫描线的编码装置输出的最大数据量限制为数量，从而增加可变长度编码方案可以实现的图像数据压缩的程度 的扫描线中未编码的图像数据。 因此，由于可变长度编码的结果，在某些类型的图像内容的情况下增加的数据量的产生被消除，从而导致编码效率的提高。

公开(公告)号：US20120139024A1

公开(公告)日：2012-06-07

申请号：US13050297

申请日：2011-03-17

申请人： Takayuki TOBA ,  Tohru Ozaki

发明人： Takayuki TOBA ,  Tohru Ozaki

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/11534 ,  H01L29/66825

摘要： In one embodiment, a nonvolatile semiconductor memory includes a memory cell array, a first silicon nitride film and a second silicon nitride film. The memory cell array includes NAND cell units. Each of the NAND cell units has memory cell transistors, a source-side select gate transistor and a drain-side select gate transistor. The source-side select gate transistors is disposed in such a manner as to face each other and the drain-side select gate transistors is disposed in such a manner as to face each other. The first silicon nitride film is present in a region between the source-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. The second silicon nitride film is formed in a region between the drain-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate.

摘要翻译： 在一个实施例中，非易失性半导体存储器包括存储单元阵列，第一氮化硅膜和第二氮化硅膜。 存储单元阵列包括NAND单元单元。 每个NAND单元单元具有存储单元晶体管，源极选择栅极晶体管和漏极侧选择栅极晶体管。 源极侧选择栅极晶体管以彼此面对的方式设置，并且漏极侧选择栅极晶体管以彼此面对的方式设置。 第一氮化硅膜存在于源极选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。 第二氮化硅膜形成在漏极侧选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。

公开(公告)号：US20100320518A1

公开(公告)日：2010-12-23

申请号：US12869502

申请日：2010-08-26

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/06

CPC分类号： H01L28/60 ,  G11C11/22 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括：晶体管，包括：源极，漏极和栅极; 源极和漏极上的第一和第二插头; 栅极上的第三个插头具有高于第一插头的顶面; 覆盖晶体管和第一至第三插头的层间绝缘膜; 层间绝缘膜上的铁电电容器，其一个电极连接到第一插头; 覆盖铁电电容器和层间绝缘膜的表面的阻挡膜，以防止影响铁电电容器的物质进入其中; 以及设置在第二和第三插头上的第四和第五插头，并且通过形成在阻挡膜中的连接孔与其连接。

公开(公告)号：US07816717B2

公开(公告)日：2010-10-19

申请号：US12020210

申请日：2008-01-25

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L21/00 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

摘要： A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides of the first gate electrode on the semiconductor substrate, and a ferroelectric capacitor provided above the memory transistor, the ferroelectric capacitor including a first electrode film connected to any one of a source and drain of the memory transistor, a second electrode film connected to the other one of the drain and source of the memory transistor, and a ferroelectric film provided between the first electrode film and the second electrode film, the memory cell section having the memory transistor and the ferroelectric capacitor connected in parallel to each other; and a select transistor section, comprising a select transistor provided at an end of the memory cell section, the select transistor including a second gate electrode provided on the semiconductor substrate with the gate insulating film interposed therebetween, and a source and drain provided at both sides of the second gate electrode on the semiconductor substrate, and a third electrode film connected to the source and drain of the select transistor and connected to a bit line via a bit line contact.

摘要翻译： 一种半导体存储器件，包括：半导体衬底; 存储单元部分，包括设置在所述半导体衬底上的存储晶体管，所述存储晶体管包括设置在所述半导体衬底上的栅极绝缘膜之间的第一栅电极，以及设置在所述第一栅电极的两侧的源极和漏极， 所述半导体衬底和设置在所述存储晶体管上方的强电介质电容器，所述强电介质电容器包括连接到所述存储晶体管的源极和漏极中的任一个的第一电极膜，连接到所述漏极和源极中的另一个的第二电极膜 以及设置在第一电极膜和第二电极膜之间的铁电体膜，具有彼此并联连接的存储晶体管和强电介质电容器的存储单元部分; 以及选择晶体管部分，包括设置在存储单元部分的一端的选择晶体管，所述选择晶体管包括设置在半导体衬底上的栅极绝缘膜之间的第二栅电极，以及设置在两侧的源极和漏极 的第二栅极电极，以及连接到选择晶体管的源极和漏极并经由位线接触连接到位线的第三电极膜。

公开(公告)号：US20100163943A1

公开(公告)日：2010-07-01

申请号：US12559358

申请日：2009-09-14

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11507 ,  H01L21/76895 ,  H01L28/55

摘要： A memory includes a first interlayer on transistors; a first and second plugs connected to the transistor; ferroelectric capacitors; a second interlayer covering a side surface of the capacitor; a local interconnection connecting the second plug to the upper electrode, wherein two upper electrodes adjacent to each other on the second plug are connected to the second plug, the lower electrodes adjacent to each other on the first plug are connected to the first plug, cell blocks comprising the connected capacitors are arranged, cell blocks adjacent to each other are arranged to be shifted by a half pitch of the local interconnection, a first gap between two capacitors adjacent to each other on the second plug is larger than twice a thickness of the second interlayer, and a second gap between the cell blocks adjacent to each other is smaller than twice the thickness of the second interlayer.

摘要翻译： 存储器包括晶体管上的第一中间层; 连接到所述晶体管的第一和第二插头; 铁电电容器; 覆盖所述电容器的侧表面的第二夹层; 将第二插头连接到上电极的局部互连，其中在第二插头上彼此相邻的两个上电极连接到第二插头，在第一插头上彼此相邻的下电极连接到第一插头单元 包括连接的电容器的块被布置成彼此相邻的单元块被布置成以局部互连的半间距偏移，在第二插头上彼此相邻的两个电容器之间的第一间隙大于 第二中间层和彼此相邻的电池块之间的第二间隙小于第二中间层的厚度的两倍。

公开(公告)号：US20090127602A1

公开(公告)日：2009-05-21

申请号：US12252451

申请日：2008-10-16

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L29/51 ,  H01L21/02 ,  G11C11/22 ,  H01L29/68

CPC分类号： H01L27/11507 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/11502 ,  H01L28/55

摘要： This disclosure concerns a memory including transistors provided on a substrate; ferroelectric capacitors provided on the transistors, the ferroelectric capacitors respectively including a ferroelectric film provided between a lower electrode and an upper electrode; and a barrier film covering a first side surface of the ferroelectric capacitor, and blocking passing of hydrogen, wherein adjacent two of the ferroelectric capacitors connected in the lower electrode form one capacitor unit, a plurality of the capacitor units connected in the upper electrode form one capacitor chain, the capacitor units are arranged with a deviation of a half pitch of the capacitor unit in adjacent plurality of capacitor chains, and when D1 is a distance between the adjacent ferroelectric capacitors within the capacitor unit, D2 is a distance between the adjacent capacitor chains, and D3 is a distance between the adjacent capacitor units within the capacitor chain, D3 is larger than D1 and D2.

摘要翻译： 本公开涉及包括设置在基板上的晶体管的存储器; 设置在晶体管上的铁电电容器，铁电电容器分别包括设置在下电极和上电极之间的铁电体膜; 以及覆盖所述强电介质电容器的第一侧面的阻挡膜和阻挡氢的通过，其中，连接在所述下部电极中的相邻的两个所述铁电电容器形成一个电容器单元，在所述上部电极中连接的多个所述电容器单元形成一个 电容器链，电容器单元在相邻的多个电容器链中以电容器单元的半间距的偏差排列，并且当D1是电容器单元内的相邻强电介质电容器之间的距离时，D2是相邻电容器之间的距离 链，D3是电容器链内的相邻电容器单元之间的距离，D3大于D1和D2。

公开(公告)号：US07312488B2

公开(公告)日：2007-12-25

申请号：US11134414

申请日：2005-05-23

申请人： Tohru Ozaki ,  Iwao Kunishima

发明人： Tohru Ozaki ,  Iwao Kunishima

IPC分类号： H01L29/76

CPC分类号： H01L27/11507 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11509 ,  H01L28/57

摘要： There is provided a semiconductor storage device comprising a ferroelectric capacitor superior in barrier capability against penetration of hydrogen from all directions including a transverse direction. The device comprises a transistor formed on a semiconductor substrate, the ferroelectric capacitor formed above the transistor and including a lower electrode, a ferroelectric film, and an upper electrode, a first hydrogen barrier film which continuously surrounds side portions of a ferroelectric capacitor cell array constituted of a plurality of ferroelectric capacitors, and a second hydrogen barrier film which is formed above the ferroelectric capacitor cell array and which is brought into contact with the first hydrogen barrier film in the whole periphery.

摘要翻译： 提供了一种包括铁电电容器的半导体存储装置，该铁电电容器的阻挡能力优于氢气从包括横向的所有方向渗透。 该器件包括形成在半导体衬底上的晶体管，形成在晶体管上方并包括下电极，铁电体膜和上电极的铁电电容器，连续围绕构成的铁电电容器单元阵列的侧部的第一氢阻挡膜 的多个强电介质电容器，以及形成在铁电体电容器单元阵列上方并与整个周边与第一氢阻挡膜接触的第二氢阻挡膜。

公开(公告)号：US20060280023A1

公开(公告)日：2006-12-14

申请号：US11440110

申请日：2006-05-25

申请人： Katsuhiko Hoya ,  Tohru Ozaki

发明人： Katsuhiko Hoya ,  Tohru Ozaki

IPC分类号： G11C8/00

CPC分类号： G11C11/22

摘要： A semiconductor memory device includes a row of memory cells connected in series, each of the memory cells including a ferroelectric capacitor and a cell transistor having a gate terminal and source/drain terminals, the source/drain terminals being connected in parallel with two electrodes of the ferroelectric capacitor, a word line connected to the gate terminal, memory cell blocks each including the row of memory cells and a block select transistor, a drain terminal of the block select transistor being connected to one end of the row of memory cells, a plate line connected to another end thereof, a bit line connected to a source terminal of the block select transistor, and a block select line connected to a gate terminal of the block select transistor, wherein a contact is provided under the plate line to connect the source terminal of the block select transistor and the bit line.

摘要翻译： 半导体存储器件包括串联连接的一行存储器单元，每个存储器单元包括铁电电容器和具有栅极端子和源极/漏极端子的单元晶体管，源极/漏极端子与两个电极 铁电电容器，连接到栅极端子的字线，每个包括行存储单元的存储单元块和块选择晶体管，块选择晶体管的漏极端子连接到该行存储单元的一端， 连接到其另一端的板线，连接到块选择晶体管的源极端的位线和连接到块选择晶体管的栅极端子的块选择线，其中在板线下方提供接触以将 块选择晶体管的源极端子和位线。

公开(公告)号：US20050205910A1

公开(公告)日：2005-09-22

申请号：US10960029

申请日：2004-10-08

申请人： Yoshinori Kumura ,  Hiroyuki Kanaya ,  Tohru Ozaki

发明人： Yoshinori Kumura ,  Hiroyuki Kanaya ,  Tohru Ozaki

IPC分类号： H01L27/105 ,  H01L21/00 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A transistor including a source/drain region is formed on a semiconductor substrate. A plug electrode is formed on the source/drain region. A conductive film is formed on the plug electrode. A first insulation film is formed on the conductive film. A lower electrode is formed on the first insulation film, and electrically connected to the conductive film formed on the plug electrode. A ferroelectric film is formed on the lower electrode. An upper electrode is formed on the ferroelectric film.

摘要翻译： 包括源极/漏极区域的晶体管形成在半导体衬底上。 插头电极形成在源极/漏极区域上。 在插头电极上形成导电膜。 在导电膜上形成第一绝缘膜。 在第一绝缘膜上形成下电极，与形成在插塞电极上的导电膜电连接。 在下电极上形成铁电体膜。 在铁电体膜上形成上部电极。