公开(公告)号：US20240203778A1

公开(公告)日：2024-06-20

申请号：US18085354

申请日：2022-12-20

Applicant: Tokyo Electron Limited

Inventor： David POWER ,  David CONKLIN ,  Anthony SCHEPIS ,  Andrew WELOTH ,  Anton DEVILLIERS

IPC: H01L21/68 ,  H01L21/67 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L21/681 ,  H01L21/67265 ,  H01L21/6835 ,  H01L23/544 ,  H01L2221/68363 ,  H01L2223/54426

Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.

公开(公告)号：US20230352343A1

公开(公告)日：2023-11-02

申请号：US18308230

申请日：2023-04-27

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  David POWER ,  Eric Chih-Fang LIU ,  Anton J. DEVILLIERS ,  Kandabara TAPILY ,  Jodi GRZESKOWIAK ,  David CONKLIN ,  Michael MURPHY

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L23/5226

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.