公开(公告)号：US5668758A

公开(公告)日：1997-09-16

申请号：US612923

申请日：1996-03-05

申请人： Tom Dang-Hsing Yiu ,  Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Teruhiko Kamei

发明人： Tom Dang-Hsing Yiu ,  Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Teruhiko Kamei

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C8/08 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C7/00

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C5/143 ,  G11C8/08

摘要： Wordline driver circuitry drives a plurality of wordlines in a flash EEPROM memory array in a first mode which selects between a positive voltage and ground, and a second mode which selects between a negative voltage and ground. A first supply voltage selector supplies positive voltage during the first mode, and a second mode reference voltage, such as ground, in the second mode. A second supply voltage selector supplies the first mode reference voltage such as ground in the first mode, and the negative voltage during a second mode. An inverting driver has an input which receives a wordline select signal, and an output coupled to the wordline, a first supply voltage input connected to the first supply voltage selector, and second supply voltage input connected to the second supply voltage selector. The inverting driver couples the first supply voltage input to the wordline when the wordline select signal is in a low state, and couples the second supply voltage input to the wordline when the wordline select signal is in a high state. A second inverter is connected in feedback across the inverting driver to hold the input of the inverting driver at the value of the wordline select signal during the negative voltage decode. The wordline select signals come from an address decoder. An isolation circuit is provided between the address decoder and the input to the inverting driver to isolate the decoder from the negative voltages which appear on the output of the second inverter during the negative voltage decoding state.

摘要翻译： PCT No.PCT / US95 / 01031 Sec。 371日期：1996年3月5日 102（e）1996年3月5日PCT 1995年1月26日PCT PCT。 公开号WO96 / 23307 日期1996年8月1日沃尔金斯司机电路以第一模式驱动闪存EEPROM存储器阵列中的多个字线，该第一模式在正电压和地之间进行选择，第二模式在负电压和地之间进行选择。 第一电源电压选择器在第一模式下提供正电压，在第二模式中提供第二模式参考电压，例如接地。 第二电源电压选择器在第一模式下提供诸如接地的第一模式参考电压，在第二模式期间提供负电压。 反相驱动器具有接收字线选择信号的输入和耦合到字线的输出，连接到第一电源电压选择器的第一电源电压输入和连接到第二电源电压选择器的第二电源电压输入。 当字线选择信号处于低状态时，反相驱动器将第一电源电压输入耦合到字线，并且当字线选择信号处于高状态时，将第二电源电压输入耦合到字线。 第二反相器通过反相驱动器反馈连接，以在负电压解码期间将反相驱动器的输入保持在字线选择信号的值。 字线选择信号来自地址解码器。 在地址解码器和反相驱动器的输入端之间设置隔离电路，以将解码器与在负电压解码状态期间出现在第二反相器的输出端上的负电压隔离。

公开(公告)号：US5691945A

公开(公告)日：1997-11-25

申请号：US605100

申请日：1996-03-01

申请人： Kong-Mou Liou ,  Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chun-Hsiung Hung ,  Ting-Chung Hu ,  Tien-Ler Lin

发明人： Kong-Mou Liou ,  Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chun-Hsiung Hung ,  Ting-Chung Hu ,  Tien-Ler Lin

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/76 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12

摘要： A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.

摘要翻译： PCT No.PCT / US95 / 06990第 371日期1996年3月1日 102（e）1996年3月1日PCT 1995年5月31日PCT PCT。 公开号WO96 / 38845 日期1996年12月5日用于提高高密度存储器件（例如闪存EEPROM）的制造成品率的灵活技术涉及重新配置具有由地址解码器选择的多个扇区的集成电路存储器阵列，以响应于N位字段 一个地址 如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器以防止对阵列中的剩余扇区的顺序寻址，同时对阵列解码器进行划分以禁用缺陷扇区。 分割步骤包括配置扇区解码器以在阵列的另一半中的另外一个扇区替换阵列的一半中的缺陷扇区，其中，当m在1和N之间时，具有与缺陷扇区相同的N个地址位的Nm -1。

公开(公告)号：US5778440A

公开(公告)日：1998-07-07

申请号：US596380

申请日：1996-02-16

申请人： Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chung-Hsiung Hung ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chung-Hsiung Hung ,  Fuchia Shone

IPC分类号： G11C16/04 ,  G11C16/32 ,  G11C16/34 ,  G06F13/00 ,  G11C16/06

CPC分类号： G11C16/0491 ,  G08G1/017 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry. Alternatively, the pattern comprises a command address which is outside the address field of the memory array. The command address may include all or only a high order segment of the actual data address. The floating gate memory includes a state machine which automatically programs and verifies programming of the block of data after the last segment of the block is detected, and may comprise a flash memory or electrically erasable programmable read only memory (EEPROM).

摘要翻译： PCT No.PCT / US95 / 06762 Sec。 371日期1996年2月16日 102（e）日期1996年2月16日PCT 1995年5月26日提交具有协议的浮动门存储器，其在检测到预定地址和/或数据模式时终止程序加载周期，提供负载循环结束的正向指示， 并消除了对受控信号中的长脉冲的要求。 响应于在输入/输出电路处接收的地址和数据段的序列，命令逻辑执行存储数据块的过程，并响应于包括至少一个的模式来检测数据块中的最后一个段 在输入/输出电路处接收的地址和数据段。 一种模式包括连续的匹配地址。 包括在命令逻辑中的模式匹配逻辑被耦合到输入/输出电路，并且存储序列中的地址，并将它们与下一个地址进行比较以指示匹配的地址。 或者，该模式包括具有对应的比较器电路的匹配地址和数据段。 或者，该模式包括在存储器阵列的地址字段之外的命令地址。 命令地址可以包括实际数据地址的全部或仅有高阶段。 浮动门存储器包括在检测到块的最后段之后自动编程和验证数据块的编程的状态机，并且可以包括闪速存储器或电可擦除可编程只读存储器（EEPROM）。

公开(公告)号：US6100557A

公开(公告)日：2000-08-08

申请号：US849561

申请日：1997-05-12

申请人： Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng

发明人： Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng

IPC分类号： H01L27/02 ,  H02M3/07 ,  H01L29/72

CPC分类号： H01L27/0222 ,  H02M3/073

摘要： An improved charge pump design is disclosed. This charge pump comprises at least one pumping transistor having a triple well arrangement. This triple pump transistor has a source and a drain region of a first conductive type formed on a first well having an opposite conductive type. A second well having the first conductive type is formed outside of the first well. The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region. Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage reduction, singly and in combination, allow the charge pump to operate more efficiently.

摘要翻译： PCT No.PCT / US96 / 16317 Sec。 371日期：1997年5月12日 102（e）日期1997年5月12日PCT提交1996年10月10日PCT公布。 公开号WO98 / 16010 PCT 日期：1998年4月16日公开了改进的电荷泵设计。 该电荷泵包括具有三阱布置的至少一个泵浦晶体管。 该三重泵晶体管具有形成在具有相反导电类型的第一阱上的第一导电类型的源区和漏区。 具有第一导电类型的第二阱形成在第一阱的外部。 源区，第一阱和第二阱被设定为基本上相同的电位。 该结构的一个方面是第一阱与漏极区形成半导体二极管。 这种布置的另一方面是晶体管的体效减小。 身体效应的降低降低了晶体管的阈值电压。 发现上述二极管和阈值电压降低，单独并且组合地允许电荷泵更有效地操作。

公开(公告)号：US5963476A

公开(公告)日：1999-10-05

申请号：US975516

申请日：1997-11-12

申请人： Chun Hsiung Hung ,  Tzeng-Huei Shiau ,  Yao-Wu Cheng ,  I-Long Lee ,  Fuchia Shone ,  Ray-Lin Wan

发明人： Chun Hsiung Hung ,  Tzeng-Huei Shiau ,  Yao-Wu Cheng ,  I-Long Lee ,  Fuchia Shone ,  Ray-Lin Wan

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/06

CPC分类号： G11C16/107 ,  G11C16/0416 ,  G11C16/16 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/115

摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.

摘要翻译： 新的闪存单元结构和操作偏置是基于使用三阱闪存单元，其允许Fowler Nordheim（F-N）一次在单元格块上进行预编程。 浮栅存储单元由具有第一导电类型的半导体衬底制成，例如p型。 包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。 还包括第一阱中的第二阱具有第一导电类型。 在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。 通道区域中包括浮动栅极和控制栅极结构。 浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除 与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。 块宽的预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。

公开(公告)号：US5754469A

公开(公告)日：1998-05-19

申请号：US718335

申请日：1996-10-01

申请人： Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng

发明人： Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C16/34 ,  G11C2211/5642

摘要： An array (10) of multi-level floating gate memory cells includes wordlines (18) connected to memory cells along a row in the array, and bit lines (12) connected to memory cells along a column in the array. A wordline voltage source (27) is included which supplies selectively wordline voltages corresponding to respective threshold voltages of the memory cells in the array. A plurality of bit latches form a page buffer (11). Bit latches are coupled to corresponding bit lines, and have a first state and a second state. The bit latches include circuits (213-216) to change the bit latches from the first state to the second state in response to signals on the corresponding bit lines that are generated in response to a wordline voltage on a selected wordline being greater than or equal to the threshold voltage of a memory cell on the corresponding bit line connected to the selected wordline. Logic (21) controls the wordline voltage source and the bit latches to apply in a sequence the wordline voltages, and to sense the state of the bit latches after applying each wordline voltage in the sequence to determine the threshold voltages of the memory cells.

摘要翻译： PCT No.PCT / US96 / 10374 Sec。 371日期：1996年10月1日 102（e）1996年10月1日PCT PCT 1996年6月14日PCT公布。 公开号WO97 / 48098 日期1997年12月18日多级浮动存储单元的阵列（10）包括连接到阵列中的行的存储单元的字线（18），以及沿列阵列的存储单元连接的位线（12） 。 包括字线电压源（27），其选择性地提供对应于阵列中的存储器单元的各个阈值电压的字线电压。 多个位锁存器形成页缓冲器（11）。 位锁存器耦合到对应的位线，并且具有第一状态和第二状态。 比特锁存器包括响应于所选择的字线上的字线电压响应于相应位线上响应的信号而将位锁存器从第一状态改变到第二状态的电路（213-216）大于或等于 到连接到所选字线的相应位线上的存储器单元的阈值电压。 逻辑（21）控制字线电压源和位锁存器以序列施加字线电压，并且在施加序列中的每个字线电压以确定存储器单元的阈值电压之后感测位锁存器的状态。

公开(公告)号：US6031757A

公开(公告)日：2000-02-29

申请号：US825879

申请日：1997-04-02

申请人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Yin-Shang Liu ,  Yao-Wu Cheng

发明人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Yin-Shang Liu ,  Yao-Wu Cheng

IPC分类号： G11C16/22 ,  G11C16/04

CPC分类号： G11C16/22

摘要： A user-programmable write protection scheme provides flexibility and superior write protect features for an integrated circuit memory which comprises an array of non-volatile erasable and programmable memory cells, including a plurality of sectors. Command logic detects command sequences indicating operations for the array, including a program operation, a sector erase operation, a read operation, a sector lock operation, and a sector unlock operation. The sector protect logic includes sector lock memory, including non-volatile memory cells that store sector lock signals for at least one sector in the array. Among other functions, the sector protect logic: 1) inhibits sector erase and program operations to a particular sector in response to a set sector lock signal corresponding to the particular sector, and to a first state of control signals in the set of control signals; 2) enables sector erase and program operations in response to a reset sector lock signal corresponding to the particular sector, and to the first state of control signals in the set of control signals; 3) inhibits sector erase and program operations to the particular sector independent of the sector lock signal in response to a second state of control signals in the set of control signals; and 4) enables sector erase and program operations independent of the sector lock signal in response to a third state of control signals in the set of control signals.

摘要翻译： PCT No.PCT / US96 / 18674 Sec。 371日期1997年4月2日 102（e）日期1997年4月2日PCT提交1996年11月22日PCT公布。 第WO98 / 22950号公报 日期1998年5月28日用户可编程写保护方案为集成电路存储器提供灵活性和出色的写保护功能，其包括包括多个扇区的非易失性可擦除和可编程存储器单元的阵列。 命令逻辑检测指示阵列的操作的命令序列，包括程序操作，扇区擦除操作，读取操作，扇区锁定操作和扇区解锁操作。 扇区保护逻辑包括扇区锁定存储器，包括存储阵列中的至少一个扇区的扇区锁定信号的非易失性存储器单元。 在其他功能中，扇区保护逻辑：1）响应于对应于特定扇区的设置扇区锁定信号，以及控制信号组中的控制信号的第一状态，禁止对特定扇区的扇区擦除和编程操作; 2）响应于对应于特定扇区的复位扇区锁定信号和控制信号组中的控制信号的第一状态使能扇区擦除和编程操作; 3）响应于该组控制信号中的控制信号的第二状态，禁止与扇区锁定信号无关的扇区擦除和编程操作到特定扇区; 和4）响应于该组控制信号中的控制信号的第三状态，使扇区擦除和编程操作独立于扇区锁定信号。