公开(公告)号：US5778440A

公开(公告)日：1998-07-07

申请号：US596380

申请日：1996-02-16

申请人： Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chung-Hsiung Hung ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chung-Hsiung Hung ,  Fuchia Shone

IPC分类号： G11C16/04 ,  G11C16/32 ,  G11C16/34 ,  G06F13/00 ,  G11C16/06

CPC分类号： G11C16/0491 ,  G08G1/017 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry. Alternatively, the pattern comprises a command address which is outside the address field of the memory array. The command address may include all or only a high order segment of the actual data address. The floating gate memory includes a state machine which automatically programs and verifies programming of the block of data after the last segment of the block is detected, and may comprise a flash memory or electrically erasable programmable read only memory (EEPROM).

摘要翻译： PCT No.PCT / US95 / 06762 Sec。 371日期1996年2月16日 102（e）日期1996年2月16日PCT 1995年5月26日提交具有协议的浮动门存储器，其在检测到预定地址和/或数据模式时终止程序加载周期，提供负载循环结束的正向指示， 并消除了对受控信号中的长脉冲的要求。 响应于在输入/输出电路处接收的地址和数据段的序列，命令逻辑执行存储数据块的过程，并响应于包括至少一个的模式来检测数据块中的最后一个段 在输入/输出电路处接收的地址和数据段。 一种模式包括连续的匹配地址。 包括在命令逻辑中的模式匹配逻辑被耦合到输入/输出电路，并且存储序列中的地址，并将它们与下一个地址进行比较以指示匹配的地址。 或者，该模式包括具有对应的比较器电路的匹配地址和数据段。 或者，该模式包括在存储器阵列的地址字段之外的命令地址。 命令地址可以包括实际数据地址的全部或仅有高阶段。 浮动门存储器包括在检测到块的最后段之后自动编程和验证数据块的编程的状态机，并且可以包括闪速存储器或电可擦除可编程只读存储器（EEPROM）。

公开(公告)号：US5745410A

公开(公告)日：1998-04-28

申请号：US619485

申请日：1996-03-21

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

IPC分类号： G11C11/40

CPC分类号： G11C11/40

摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。 第WO97 / 19452号公报 日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。 本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。 在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。 在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。 在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

公开(公告)号：US5691945A

公开(公告)日：1997-11-25

申请号：US605100

申请日：1996-03-01

申请人： Kong-Mou Liou ,  Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chun-Hsiung Hung ,  Ting-Chung Hu ,  Tien-Ler Lin

发明人： Kong-Mou Liou ,  Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chun-Hsiung Hung ,  Ting-Chung Hu ,  Tien-Ler Lin

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/76 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12

摘要： A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.

摘要翻译： PCT No.PCT / US95 / 06990第 371日期1996年3月1日 102（e）1996年3月1日PCT 1995年5月31日PCT PCT。 公开号WO96 / 38845 日期1996年12月5日用于提高高密度存储器件（例如闪存EEPROM）的制造成品率的灵活技术涉及重新配置具有由地址解码器选择的多个扇区的集成电路存储器阵列，以响应于N位字段 一个地址 如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器以防止对阵列中的剩余扇区的顺序寻址，同时对阵列解码器进行划分以禁用缺陷扇区。 分割步骤包括配置扇区解码器以在阵列的另一半中的另外一个扇区替换阵列的一半中的缺陷扇区，其中，当m在1和N之间时，具有与缺陷扇区相同的N个地址位的Nm -1。

公开(公告)号：US5668758A

公开(公告)日：1997-09-16

申请号：US612923

申请日：1996-03-05

申请人： Tom Dang-Hsing Yiu ,  Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Teruhiko Kamei

发明人： Tom Dang-Hsing Yiu ,  Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Teruhiko Kamei

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C8/08 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C7/00

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C5/143 ,  G11C8/08

摘要： Wordline driver circuitry drives a plurality of wordlines in a flash EEPROM memory array in a first mode which selects between a positive voltage and ground, and a second mode which selects between a negative voltage and ground. A first supply voltage selector supplies positive voltage during the first mode, and a second mode reference voltage, such as ground, in the second mode. A second supply voltage selector supplies the first mode reference voltage such as ground in the first mode, and the negative voltage during a second mode. An inverting driver has an input which receives a wordline select signal, and an output coupled to the wordline, a first supply voltage input connected to the first supply voltage selector, and second supply voltage input connected to the second supply voltage selector. The inverting driver couples the first supply voltage input to the wordline when the wordline select signal is in a low state, and couples the second supply voltage input to the wordline when the wordline select signal is in a high state. A second inverter is connected in feedback across the inverting driver to hold the input of the inverting driver at the value of the wordline select signal during the negative voltage decode. The wordline select signals come from an address decoder. An isolation circuit is provided between the address decoder and the input to the inverting driver to isolate the decoder from the negative voltages which appear on the output of the second inverter during the negative voltage decoding state.

摘要翻译： PCT No.PCT / US95 / 01031 Sec。 371日期：1996年3月5日 102（e）1996年3月5日PCT 1995年1月26日PCT PCT。 公开号WO96 / 23307 日期1996年8月1日沃尔金斯司机电路以第一模式驱动闪存EEPROM存储器阵列中的多个字线，该第一模式在正电压和地之间进行选择，第二模式在负电压和地之间进行选择。 第一电源电压选择器在第一模式下提供正电压，在第二模式中提供第二模式参考电压，例如接地。 第二电源电压选择器在第一模式下提供诸如接地的第一模式参考电压，在第二模式期间提供负电压。 反相驱动器具有接收字线选择信号的输入和耦合到字线的输出，连接到第一电源电压选择器的第一电源电压输入和连接到第二电源电压选择器的第二电源电压输入。 当字线选择信号处于低状态时，反相驱动器将第一电源电压输入耦合到字线，并且当字线选择信号处于高状态时，将第二电源电压输入耦合到字线。 第二反相器通过反相驱动器反馈连接，以在负电压解码期间将反相驱动器的输入保持在字线选择信号的值。 字线选择信号来自地址解码器。 在地址解码器和反相驱动器的输入端之间设置隔离电路，以将解码器与在负电压解码状态期间出现在第二反相器的输出端上的负电压隔离。

公开(公告)号：US5963476A

公开(公告)日：1999-10-05

申请号：US975516

申请日：1997-11-12

申请人： Chun Hsiung Hung ,  Tzeng-Huei Shiau ,  Yao-Wu Cheng ,  I-Long Lee ,  Fuchia Shone ,  Ray-Lin Wan

发明人： Chun Hsiung Hung ,  Tzeng-Huei Shiau ,  Yao-Wu Cheng ,  I-Long Lee ,  Fuchia Shone ,  Ray-Lin Wan

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/06

CPC分类号： G11C16/107 ,  G11C16/0416 ,  G11C16/16 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/115

摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.

摘要翻译： 新的闪存单元结构和操作偏置是基于使用三阱闪存单元，其允许Fowler Nordheim（F-N）一次在单元格块上进行预编程。 浮栅存储单元由具有第一导电类型的半导体衬底制成，例如p型。 包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。 还包括第一阱中的第二阱具有第一导电类型。 在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。 通道区域中包括浮动栅极和控制栅极结构。 浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除 与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。 块宽的预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。

公开(公告)号：US5699298A

公开(公告)日：1997-12-16

申请号：US718525

申请日：1996-10-07

申请人： Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Yuan-Chang Liu ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Han Sung Chen ,  Fuchia Shone

发明人： Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Yuan-Chang Liu ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Han Sung Chen ,  Fuchia Shone

IPC分类号： G11C16/16 ,  G11C16/30 ,  G11C16/00

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/30

摘要： Substantial reduction in peak current encountered during an erase process for a flash memory device is achieved by selection of source voltage potential during the erase according to the expected band-to-band tunneling current encountered during the process. During the beginning of the process, a lower source voltage potential is selected, which is high enough to cause significant erasing while suppressing band-to-band tunneling current in a portion of the array, and during a second part of the erasing process, a higher source potential is utilized, which ensures successful erasing of the array, without exceeding the peak current requirements of the power supply used with the device. The first and second parts of the erase sequence will induce band-to-band tunneling current in addition to Fowler-Nordheim tunneling current. The band-to-band tunneling current is characterized by a turn on threshold source potential which is inversely related to the threshold of the cell receiving the voltage sequence. The source voltage used in the first part of the erase sequence is set at level that is near or above the turn on threshold source potential for higher threshold cells that are in the high threshold state, but less than the turn on threshold source potential for lower threshold cells in the high threshold state. The source potential in the second part is set at level which is near or above the turn on threshold source potential for lower threshold cells in the high threshold state.

摘要翻译： PCT No.PCT / US96 / 07490 Sec。 371日期1996年10月7日第 102（e）1996年10月7日PCT 1996年5月22日提交闪速存储器件的擦除过程中遇到的峰值电流的实质性降低是通过根据预期的带 - 带来在擦除期间选择源极电压电位来实现的 过程中遇到的隧道电流。 在该过程开始时，选择较低的源极电压电位，其足够高以引起显着擦除，同时抑制阵列的一部分中的带间隧穿电流，并且在擦除处理的第二部分期间， 利用更高的源极电位，确保阵列的成功擦除，而不超过与器件一起使用的电源的峰值电流要求。 擦除序列的第一部分和第二部分除了Fowler-Nordheim隧道电流之外还将引起带间隧穿电流。 带 - 带隧穿电流的特征在于开启阈值源极电位，其与接收电压序列的电池的阈值成反比。 在擦除序列的第一部分中使用的源电压被设置为接近或高于处于高阈值状态的较高阈值电池的阈值源极电位的接通或高于电平，但小于阈值源电位的导通电平较低 阈值细胞处于高阈值状态。 第二部分中的源极电位被设置在接近或高于阈值电位的阈值源电位的接通或高于在高阈值状态下的较低阈值电池的电位。

公开(公告)号：US06400634B1

公开(公告)日：2002-06-04

申请号：US09029952

申请日：1999-06-18

申请人： Kong-Mou Liou ,  Ting-Chung Hu ,  Ray-Lin Wan ,  Fuchia Shone

发明人： Kong-Mou Liou ,  Ting-Chung Hu ,  Ray-Lin Wan ,  Fuchia Shone

IPC分类号： G11C800

CPC分类号： G11C16/3495 ,  G11C16/08

摘要： A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. A record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.

摘要翻译： 一种方法提高了存储器单元阵列的耐久性，其具有根据存储器单元在性能容限内可以承受的变化周期的数量来指定的耐久性。 该方法基于将阵列布置成多个扇区，并且分配用于存储数据结构的地址的子集，其预期将改变足以超过阵列中的存储器单元的指定耐久性的次数。 保持指示多个扇区中的一个作为当前扇区的记录，将使用地址子集的访问定向到当前扇区，对对当前扇区的地址子集标识的存储器单元进行计数改变，以及改变当前扇区 当变化的计数超过阈值时，到多个扇区中的另一个扇区。

公开(公告)号：US6100557A

公开(公告)日：2000-08-08

申请号：US849561

申请日：1997-05-12

申请人： Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng

发明人： Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng

IPC分类号： H01L27/02 ,  H02M3/07 ,  H01L29/72

CPC分类号： H01L27/0222 ,  H02M3/073

摘要： An improved charge pump design is disclosed. This charge pump comprises at least one pumping transistor having a triple well arrangement. This triple pump transistor has a source and a drain region of a first conductive type formed on a first well having an opposite conductive type. A second well having the first conductive type is formed outside of the first well. The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region. Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage reduction, singly and in combination, allow the charge pump to operate more efficiently.

摘要翻译： PCT No.PCT / US96 / 16317 Sec。 371日期：1997年5月12日 102（e）日期1997年5月12日PCT提交1996年10月10日PCT公布。 公开号WO98 / 16010 PCT 日期：1998年4月16日公开了改进的电荷泵设计。 该电荷泵包括具有三阱布置的至少一个泵浦晶体管。 该三重泵晶体管具有形成在具有相反导电类型的第一阱上的第一导电类型的源区和漏区。 具有第一导电类型的第二阱形成在第一阱的外部。 源区，第一阱和第二阱被设定为基本上相同的电位。 该结构的一个方面是第一阱与漏极区形成半导体二极管。 这种布置的另一方面是晶体管的体效减小。 身体效应的降低降低了晶体管的阈值电压。 发现上述二极管和阈值电压降低，单独并且组合地允许电荷泵更有效地操作。

公开(公告)号：US5754469A

公开(公告)日：1998-05-19

申请号：US718335

申请日：1996-10-01

申请人： Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng

发明人： Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C16/34 ,  G11C2211/5642

摘要： An array (10) of multi-level floating gate memory cells includes wordlines (18) connected to memory cells along a row in the array, and bit lines (12) connected to memory cells along a column in the array. A wordline voltage source (27) is included which supplies selectively wordline voltages corresponding to respective threshold voltages of the memory cells in the array. A plurality of bit latches form a page buffer (11). Bit latches are coupled to corresponding bit lines, and have a first state and a second state. The bit latches include circuits (213-216) to change the bit latches from the first state to the second state in response to signals on the corresponding bit lines that are generated in response to a wordline voltage on a selected wordline being greater than or equal to the threshold voltage of a memory cell on the corresponding bit line connected to the selected wordline. Logic (21) controls the wordline voltage source and the bit latches to apply in a sequence the wordline voltages, and to sense the state of the bit latches after applying each wordline voltage in the sequence to determine the threshold voltages of the memory cells.

摘要翻译： PCT No.PCT / US96 / 10374 Sec。 371日期：1996年10月1日 102（e）1996年10月1日PCT PCT 1996年6月14日PCT公布。 公开号WO97 / 48098 日期1997年12月18日多级浮动存储单元的阵列（10）包括连接到阵列中的行的存储单元的字线（18），以及沿列阵列的存储单元连接的位线（12） 。 包括字线电压源（27），其选择性地提供对应于阵列中的存储器单元的各个阈值电压的字线电压。 多个位锁存器形成页缓冲器（11）。 位锁存器耦合到对应的位线，并且具有第一状态和第二状态。 比特锁存器包括响应于所选择的字线上的字线电压响应于相应位线上响应的信号而将位锁存器从第一状态改变到第二状态的电路（213-216）大于或等于 到连接到所选字线的相应位线上的存储器单元的阈值电压。 逻辑（21）控制字线电压源和位锁存器以序列施加字线电压，并且在施加序列中的每个字线电压以确定存储器单元的阈值电压之后感测位锁存器的状态。

公开(公告)号：US06219290B1

公开(公告)日：2001-04-17

申请号：US09172274

申请日：1998-10-14

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  I-Long Lee ,  Yin-Shang Liu ,  Ray-Lin Wan

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  I-Long Lee ,  Yin-Shang Liu ,  Ray-Lin Wan

IPC分类号： G11C702

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/28

摘要： A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.

摘要翻译： 描述了用于感测最小化读取时间的存储单元的逻辑状态的感测电路，其包括对应于阵列电路路径的第一电路支路和对应于参考单元电路路径的第二电路支路。 在预解码间隔期间的操作中，在第一电路路径中启用额外的负载和电流产生电路，使得感测电路比较器的感测输入所看到的电压被驱动为基本上等于参考信号的电压，如 由参考单元电路路径建立在感测电路比较器的参考输入端上。 一旦解码了地址，则禁用附加负载电路，以便允许比较器的感测输入转换到代表存储在存储单元中的逻辑状态的电压。