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1.发明授权Super integration circuit device having a plurality of IC-chip equivalent regions formed on a single semiconductor substrate 失效具有形成在单个半导体衬底上的多个IC芯片等效区域的超级积分电路器件
公开(公告)号：US4814639A
公开(公告)日：1989-03-21
申请号：US238998
申请日：1988-08-29
IPC分类号： H01L21/822 , G01R31/28 , G01R31/3185 , H01L21/66 , H01L21/82 , H01L27/04 , H03K3/26 , H03K17/56
CPC分类号： G01R31/318513 , G01R31/2884 , G01R31/318505 , Y10S257/923
摘要： At least first and second IC-chip equivalent regions having functions available from conventional one-chip IC device are formed on a single semiconductor substrate. An output of the second region is supplied to an input terminal of the first region. The output of the second region is also delivered at an external terminal in response to a test signal through a multiplexer or a bidirectional buffer.
摘要翻译： 至少具有可从常规单片IC器件获得的功能的第一和第二IC芯片等效区域形成在单个半导体衬底上。 第二区域的输出被提供给第一区域的输入端子。 响应于通过复用器或双向缓冲器的测试信号，第二区域的输出也在外部端子处传送。
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公开(公告)号：US4551716A
公开(公告)日：1985-11-05
申请号：US390046
申请日：1982-06-18
申请人： Tomotaka Saito , Kenichi Nagao
发明人： Tomotaka Saito , Kenichi Nagao
CPC分类号： G09G3/18 , G06F3/0489
摘要： An electronic calculator includes a display section having segment LCDs, a key-in section having a plurality of key switches arranged in a matrix, and a one chip integrated calculation control unit connected to the display section and the key-in section for performing a calculation and a display in accordance with a key input signal. In the calculation control unit of the calculator, a common terminal is used for both a key output signal for detecting the key input signal and a segment signal for driving the display section. The common terminal is so set as to have a high impedance when the key switch is still closed after the end of one time processing of the key input signal.
摘要翻译： 电子计算器包括具有段LCD的显示部分，具有以矩阵形式布置的多个键开关的键入部分和连接到显示部分和用于执行计算的键入部分的单芯片集成计算控制单元 以及根据键输入信号的显示。 在计算器的计算控制单元中，公共端用于检测键输入信号的键输出信号和用于驱动显示部的段信号。 当钥匙输入信号的一次处理结束后钥匙开关仍然关闭时，公共端子被设定为具有高阻抗。
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公开(公告)号：US5057702A
公开(公告)日：1991-10-15
申请号：US457875
申请日：1989-12-27
申请人： Nobutaka Kitagawa , Hiroki Muroga , Tomotaka Saito
发明人： Nobutaka Kitagawa , Hiroki Muroga , Tomotaka Saito
CPC分类号： H03K5/1565
摘要： An integrating circuit integrates an input signal. When an output from the integrating circuit is input to an AC coupling circuit, only an AC component of the output is extracted. The AC component which passes through the AC coupling circuit is waveshaped and coverted into a rectangular wave by a waveshaping circuit. The duty ratio of the waveshaped rectangular wave is detected by a duty ratio detecting circuit. A voltage corresponding to the duty ratio is then generated and fed back to the output of the AC coupling circuit through a feedback circuit. As a result, a DC bias component is applied to the AC component which has passed through the AC coupling circuit. In this case, the voltage generated by the duty ratio detecting circuit is controlled to coincide with the circuit threshold value of the waveshaping circuit, and a rectangular wave having a duty ratio of 50% is output from the waveshaping circuit.
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4.发明授权Instruction code conversion unit and information processing system and instruction code generation method 有权指令代码转换单元和信息处理系统及指令代码生成方法公开(公告)号：US06801996B2
公开(公告)日：2004-10-05
申请号：US09778069
申请日：2001-02-07
申请人： Moriyasu Banno , Tomoaki Shoda , Hiroshi Itaya , Tomotaka Saito
发明人： Moriyasu Banno , Tomoaki Shoda , Hiroshi Itaya , Tomotaka Saito
IPC分类号： G06F932
CPC分类号： G06F9/30178
摘要： An instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes which are converted by the instruction code conversion unit are described. The efficiency of coding of the program is improved by making use of an existing processor as selected is used without modification. An instruction code conversion unit performs conversion of the address of a native instruction code to the address of the corresponding compressed instruction code in a program memory by shifting the address of the native instruction code as outputted from the processor to the right by one bit.
摘要翻译： 指令代码转换单元，设置有指令代码转换单元的信息处理系统和用于产生由指令代码转换单元转换的指令代码的指令代码生成方法。 通过使用未经修改地选择的现有处理器来改进程序的编码效率。 指令代码转换单元通过将从处理器输出的本地指令代码的地址向右移位一位，来执行本地指令代码的地址到程序存储器中对应的压缩指令代码的地址的转换。
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公开(公告)号：US4641278A
公开(公告)日：1987-02-03
申请号：US666449
申请日：1984-10-30
申请人： Tomotaka Saito
发明人： Tomotaka Saito
CPC分类号： G06F9/30032
摘要： A memory device with a register interchange function includes a register file with a plurality of registers, one of which is selected according to select signals, and a register select circuit. The internal memory state of the register select circuit is updated according to the internal memory state and a pair of interchange data for interchanging the select signals. In a register selection mode, a level setting of the select data is performed depending on the internal memory state and the register select data.
摘要翻译： 具有寄存器交换功能的存储器件包括具有多个寄存器的寄存器文件，其中一个寄存器根据选择信号被选择，寄存器选择电路。 根据内部存储器状态更新寄存器选择电路的内部存储器状态，以及一对用于交换选择信号的互换数据。 在寄存器选择模式中，根据内部存储器状态和寄存器选择数据执行选择数据的电平设置。
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公开(公告)号：US4583092A
公开(公告)日：1986-04-15
申请号：US558477
申请日：1983-12-06
申请人： Tomotaka Saito
发明人： Tomotaka Saito
CPC分类号： H03K17/6871 , H03M11/20
摘要： A sweep circuit of a key matrix, has an output circuit wherein a series circuit of a pair of transistors with a terminal interposed therebetween is inserted between a power supply and a reference potential, and a timing pulse for selectively turning on one of said pair of transistors is supplied to the gates of the pair of transistors so as to produce a key scanning signal; an input circuit wherein a transistor is inserted between a terminal connecting an output side of the key matrix and the reference potential, the key matrix being connected between the terminals of the output and input circuits; and a transistor which switches to insert a current limiting resistor between the reference potential and the transistor at the reference potential side in each of the input and output circuits in the non-read-in mode.
摘要翻译： 按键矩阵的扫描电路具有输出电路，其中一对晶体管的串联电路插入在电源和参考电位之间，并且定时脉冲用于选择性地导通所述一对 晶体管被提供给该对晶体管的栅极，以产生键扫描信号; 一个输入电路，其中一个晶体管被插在连接在键矩阵的一个输出端的一个终端和该参考电位之间，该键矩阵连接在输出和输入电路的端子之间; 以及晶体管，其切换以在非读入模式下在每个输入和输出电路中的参考电位和参考电位侧的晶体管之间插入限流电阻。
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公开(公告)号：US5307313A
公开(公告)日：1994-04-26
申请号：US659506
申请日：1991-02-22
申请人： Akihiro Yamazaki , Tomotaka Saito , Shuichi Ito
发明人： Akihiro Yamazaki , Tomotaka Saito , Shuichi Ito
IPC分类号： G11C29/14 , G01R31/317 , G06F1/24 , G06F11/22 , G06F13/26 , G06F15/78 , G11C17/00 , G11C29/00 , G11C8/02
CPC分类号： G06F13/26 , G01R31/31701
摘要： In a semiconductor integrated circuit for switching various functions in accordance with "H"/"L" level of a read output from EPROM cells or the like, a state of memory cells incorporated in the semiconductor is detected to switch a function state. The semiconductor integrated circuit is free from an inoperative state caused by indefinite values of an initial state (erasure state) as of the EPROM cells and the like, or is free from a state in which only a predetermined operation is performed. When a writing operation is performed to EPROM cells and the like in an initial state in advance, a function test for a semiconductor integrated circuit can be normally performed. A test time can be largely decreased compared with that of a conventional technique, and a production cost can be largely reduced.
摘要翻译： 在用于根据EPROM单元等的读取输出的“H”/“L”电平切换各种功能的半导体集成电路中，检测结合在半导体中的存储单元的状态以切换功能状态。 半导体集成电路没有由EPROM单元等的初始状态（擦除状态）的不确定值引起的不工作状态，或者不存在仅执行预定操作的状态。 当预先在初始状态下对EPROM单元等进行写入操作时，可以正常地进行半导体集成电路的功能测试。 与常规技术相比，测试时间可以大大降低，并且可以大大降低生产成本。
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公开(公告)号：US5239194A
公开(公告)日：1993-08-24
申请号：US661816
申请日：1991-02-28
IPC分类号： H01L27/02
CPC分类号： H01L27/0266
摘要： A semiconductor substrate has a plurality of MOS transistors formed therein. Each of the transistors comprises high density diffusion regions having high impurity density and serving as source and drain, low density diffusion regions having low impurity density and extending in contact with the high density diffusion regions, respectively, a channel region formed between the low density diffusion regions, and a gate formed above the substrate and insulated from the channel region. One of the transistors has its drain connected to an input/output terminal. The low density diffusion region of the one has impurity density higher than that of the other. The channel length of the one is greater than that of the other.
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公开(公告)号：US5138190A
公开(公告)日：1992-08-11
申请号：US406092
申请日：1989-09-12
申请人： Akihiro Yamazaki , Tomotaka Saito
发明人： Akihiro Yamazaki , Tomotaka Saito
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L29/788 , H01L29/792 , H02M3/07 , H03K17/693 , H03K19/094 , H03K19/0952
CPC分类号： H02M3/07 , G11C16/30 , G11C5/145 , H03K17/693
摘要： A charge pump circuit including a step-up section (1) having an output point to which a load is connected, the step-up section (1 ) having a function to step up an output potential from a predetermined potential lower than a potential (V.sub.PP) of a power supply to a desired potential higher than the power supply potential (V.sub.PP), wherein the charge pump circuit comprises initial potential setting switch (N.sub.10) connected between the power supply and the output point of the step-up section (1), and operative so that it is turned on with the beginning of the step-up operation of the step-up section (1) to propagate the power supply potential (V.sub.PP) to the output point of the step-up section (1), and that it is turned off in a suitable time. With the beginning of the step-up operation of the step-up section (1), the initial potential setting switch (N.sub.10) is turned on. As a result, a power supply potential (V.sub.PP) is propagated to the output point of the step-up section (1). Thus, the output potential is initially set to a relatively high potential obtained by subtracting a voltage drop of the initial potential setting switch (N.sub.10) from the power supply potential (V.sub.PP). When the output of the step-up section (1) rises to some extent in a suitable time, the initial potential setting switch (N.sub.10) is turned off. After that, the step-up section (1) delivers a voltage to the load.
摘要翻译： 一种电荷泵电路，包括具有连接负载的输出点的升压部分（1），所述升压部分（1）具有将预定电位低于电位的输出电位升高的功能（ VPP），其中所述电荷泵电路包括连接在所述电源和所述升压部（1）的输出点之间的初始电位设定开关（N10） ），并且使其在升压部（1）的升压操作开始时被接通，以将电源电位（VPP）传播到升压部（1）的输出点， ，并在适当的时间关闭。 随着升压部（1）的升压动作开始，初始电位设定开关（N10）接通。 结果，电源电位（VPP）被传播到升压部（1）的输出点。 因此，输出电位初始设定为通过从电源电位（VPP）减去初始电位设定开关（N10）的电压降而获得的较高电位。 当升压部分（1）的输出在合适的时间内上升到某种程度时，初始电位设定开关（N10）关闭。 之后，升压部分（1）向负载传送电压。
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公开(公告)号：US5041744A
公开(公告)日：1991-08-20
申请号：US374069
申请日：1989-06-30
申请人： Hideo Sakai , Tomotaka Saito
发明人： Hideo Sakai , Tomotaka Saito
IPC分类号： H03K5/08 , H03F3/345 , H03K5/24 , H03K19/096
摘要： The present invention provides a logic circuit comprising a first power terminal, a second power terminal set at a higher potential than the first power terminal, a first FET of a first conductivity having a current path coupled to the first power terminal, a second FET of a second conductivity having a current path coupled to the second power terminal, and an input terminal commonly coupled to gate terminals of the first and second FETs, the first FET and the second FET having a relationship expressed approximately by the following equation: ##EQU1## where R.sub.S is a resistance of a resistor element parasitically produced between the first power terminal and the current path of the first FET. R.sub.D is a resistance of a resistor element parasitically produced between the second power terminal and the current path of the second FET, W.sub.N is a channel width of the first FET, W.sub.P is a channel width of the second FET, L.sub.N is a channel length of the first FET, L.sub.P is a channel length of the second FET, .mu..sub.N is a first carrier mobililty of the first FET, and .mu..sub.P is a second carrier mobility of the second FET.
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