公开(公告)号：US06850437B2

公开(公告)日：2005-02-01

申请号：US10781921

申请日：2004-02-20

申请人： Tadayuki Taura ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Tadayuki Taura ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G01R1/06 ,  G01R31/28 ,  G11C16/02 ,  G11C16/06 ,  G11C16/20 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  G11C29/34

CPC分类号： G11C29/846 ,  G11C16/20 ,  G11C2029/1208

摘要： A nonvolatile semiconductor memory device includes a first memory cell array including electrically re-programmable main memory cells, a second memory cell array including electrically data-programmable redundancy memory cells, a first storage configured to store a specified code, a first comparator configured to compare a selected code with the specified code to generate an activating signal, a faulty address latch circuit configured to be activated by the activating signal and controlled to temporarily latch a fault address corresponding to the fault, a second storage configured to store the faulty address latched by the faulty address latch circuit, a second comparator configured to compare an input address with the faulty address to generate a replacement control signal when the input address coincides with the faulty address, and a replacing circuit configured to replace an output of the first memory cell array with an output of the second memory cell array.

摘要翻译： 非易失性半导体存储器件包括包括电可重新编程的主存储器单元的第一存储单元阵列，包括电数据可编程冗余存储器单元的第二存储单元阵列，被配置为存储指定代码的第一存储器，配置为比较的第一比较器 具有指定代码的选择代码以产生激活信号，故障地址锁存电路被配置为由激活信号激活并被控制以临时锁存与该故障相对应的故障地址;第二存储器，被配置为存储由该故障锁存的故障地址 故障地址锁存电路，第二比较器，被配置为当输入地址与故障地址一致时，将输入地址与故障地址进行比较，以产生替换控制信号;以及替换电路，被配置为替换第一存储单元阵列的输出 具有第二存储单元阵列的输出。

公开(公告)号：US06801457B2

公开(公告)日：2004-10-05

申请号：US10665014

申请日：2003-09-22

申请人： Toru Tanzawa ,  Shigeru Atsumi

发明人： Toru Tanzawa ,  Shigeru Atsumi

IPC分类号： G11C1604

CPC分类号： G11C11/5635 ,  G11C7/06 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/344 ,  G11C2211/5641 ,  G11C2211/565

摘要： A non-volatile semiconductor memory comprises a memory cell array having a plurality of non-volatile memory cells, at least one reference cell, a read circuit for reading data by applying a first voltage to one of word lines to compare a current flowing through one of bit lines with a current flowing through the reference cell, an erase circuit for erasing the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells, first and second regulators, and an erase verify circuit for detecting whether the erase has finished by applying an output voltage of the first regulator to word lines of the memory cells to be erased, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.

公开(公告)号：US06711057B2

公开(公告)日：2004-03-23

申请号：US10234704

申请日：2002-09-05

申请人： Tadayuki Taura ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Tadayuki Taura ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G11C1606

CPC分类号： G11C29/846 ,  G11C16/20 ,  G11C2029/1208

摘要： A nonvolatile semiconductor memory device comprises a first memory cell array including electrically re-programmable main memory cells, a second memory cell array including electrically data-programmable redundancy memory cells, a first storage configured to store a specified code, a first comparator configured to compare a selected code with the specified code to generate an activating signal, a faulty address latch circuit configured to be activated by the activating signal and controlled to temporarily latch a fault address corresponding to the fault, a second storage configured to store the faulty address latched by the faulty address latch circuit, a second comparator configured to compare an input address with the faulty address to generate a replacement control signal when the input address coincides with the faulty address, and a replacing circuit configured to replace an output of the first memory cell array with an output of the second memory cell array.

摘要翻译： 非易失性半导体存储器件包括包括电可重新编程的主存储器单元的第一存储单元阵列，包括电数据可编程冗余存储器单元的第二存储单元阵列，被配置为存储指定代码的第一存储器，被配置为比较的第一比较器 具有指定代码的选择代码以产生激活信号，故障地址锁存电路被配置为由激活信号激活并被控制以临时锁存与该故障相对应的故障地址;第二存储器，被配置为存储由该故障锁存的故障地址 故障地址锁存电路，第二比较器，被配置为当输入地址与故障地址一致时，将输入地址与故障地址进行比较，以产生替换控制信号;以及替换电路，被配置为替换第一存储单元阵列的输出 具有第二存储单元阵列的输出。

公开(公告)号：US06671203B2

公开(公告)日：2003-12-30

申请号：US10233133

申请日：2002-08-30

申请人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

发明人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

IPC分类号： G11C1604

CPC分类号： G11C16/0408 ,  G11C16/08 ,  G11C16/26 ,  G11C29/70

摘要： A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.

摘要翻译： 非易失性半导体存储器包括第一和第二非易失性存储器组，用于读取的数据线，用于编程和验证的数据线，用于读取的读出放大器，用于编程和验证的读出放大器以及程序电路。 数据线布置在第一和第二非易失性存储体之间的区域中，并且选择性地连接到第一和第二非易失性存储体的位线。 用于读取的读出放大器连接到数据线进行读取。 用于程序和验证的读出放大器和程序电路连接到数据线进行程序和验证。

公开(公告)号：US06337825B2

公开(公告)日：2002-01-08

申请号：US09813811

申请日：2001-03-22

申请人： Toru Tanzawa ,  Shigeru Atsumi

发明人： Toru Tanzawa ,  Shigeru Atsumi

IPC分类号： G11C702

CPC分类号： G11C16/28

摘要： In a semiconductor memory device enabling to lower the source voltage, bit lines (BL) of a memory cell array (11) are selected by a column gate (12) and connected to sense amplifiers (13). Each sense amplifier (13) includes an operational amplifier (OP) having a sense node (SA) as one of its input terminals and a reference node (RE)to be shared with other sense amplifiers (13) as its other input terminal, an NMOS transistor (QN01) as a current source load interposed between the sense node (SA) and a power source (VCC) for each operational amplifier (OP), an NMOS transistor (QN02) as a current source load interposed between the reference node (REF) and the power source (VCC) for each operational amplifier (OP), and a reference voltage generating circuit (21) connected to the reference node (REF) and shared with other sense amplifiers (13) to generate a reference voltage of an intermediate level between voltages of two-valued data output to the sense node SA.

摘要翻译： 在能够降低源极电压的半导体存储器件中，存储单元阵列（11）的位线（BL）由列栅极（12）选择并连接到读出放大器（13）。 每个读出放大器（13）包括具有感测节点（SA）作为其输入端之一的运算放大器（OP）和作为其另一输入端与其它读出放大器（13）共用的参考节点（RE）， 作为用于每个运算放大器（OP）的感测节点（SA）和电源（VCC）之间的电流源负载的NMOS晶体管（QN01），作为当前源负载的NMOS晶体管（QN02）插入参考节点 REF）和用于每个运算放大器（OP）的电源（VCC）以及连接到参考节点（REF）并与其它读出放大器（13）共享的参考电压产生电路（21），以产生基准电压 输出到感测节点SA的两值数据的电压之间的中间电平。

公开(公告)号：US06999365B2

公开(公告)日：2006-02-14

申请号：US10896701

申请日：2004-07-22

申请人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/28

摘要： A semiconductor memory device is provided using a sense amp circuitry capable of lowering a supply voltage. The semiconductor memory device includes an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from the array of memory cells with a reference voltage applied to a reference sense line to determine the data; and a reference voltage generator configured to generate the reference voltage applied to the reference sense line.

摘要翻译： 使用能够降低电源电压的读出放大器电路来提供半导体存储器件。 半导体存储器件包括存储单元阵列，每个存储器单元被配置为根据电流的存在/不存在或大小来存储数据; 感测放大器，被配置为基于从存储器单元阵列中选择的存储器单元中的数据与施加到参考感测线的参考电压比较在感测线上引起的电压以确定数据; 以及参考电压发生器，被配置为产生施加到参考感测线的参考电压。

公开(公告)号：US06788601B2

公开(公告)日：2004-09-07

申请号：US10305785

申请日：2002-11-26

申请人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G11C702

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/28

摘要： A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.

摘要翻译： 一种半导体存储器件包括存储单元阵列，一个读出放大器，和一个基准电压generator.The参考电压发生器包括含有参考单元中流动的基准电流和第一电流源负载提供电流的基准的基准电池单元 细胞; 含有参考晶体管的参考晶体管单元中流动反射基准电流和供给电流的参考晶体管的第二电流源负载的电流; 用于参考晶体管的负反馈控制的控制放大器; 电流源晶体管; 以及连接到参考感测线的第三电流源负载。

公开(公告)号：US06781879B2

公开(公告)日：2004-08-24

申请号：US10235170

申请日：2002-09-05

申请人： Toru Tanzawa ,  Shigeru Atsumi

发明人： Toru Tanzawa ,  Shigeru Atsumi

IPC分类号： G11C700

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3436 ,  G11C29/846 ,  H01L27/115

摘要： A first address subset is allocated as a first column address in a nonvolatile semiconductor memory. In addition, a second address subset higher in order than the first address subset is allocated as a first row address. Furthermore, a third address subset higher in order than the second address subset is allocated as a second column address.

摘要翻译： 第一地址子集被分配为非易失性半导体存储器中的第一列地址。 此外，分配比第一地址子集更高的第二地址子集作为第一行地址。 此外，分配比第二地址子集更高的第三地址子集作为第二列地址。

公开(公告)号：US06781439B2

公开(公告)日：2004-08-24

申请号：US10178303

申请日：2002-06-25

申请人： Toru Tanzawa ,  Shigeru Atsumi

发明人： Toru Tanzawa ,  Shigeru Atsumi

IPC分类号： G05F1575

CPC分类号： G11C5/145 ,  H02M3/07

摘要： A standby-mode booster circuit is activated in both a standby mode and an active mode and boosts up a power supply voltage to generate a booster voltage and output it from an output terminal. An active-mode booster circuit is activated in the active mode. In the active-mode booster circuit, an NMOS transistor is first turned on in response to a reset signal supplied from a reset signal generation circuit and then a connection node of capacitors is reset to the power supply voltage by the NMOS transistor. The boost operation is then started to output the booster voltage from the output terminal.

摘要翻译： 待机模式升压电路在待机模式和有功模式下都被激活，并提升电源电压以产生升压电压并从输出端输出。 在主动模式下激活主动模式升压电路。 在有源模式升压电路中，NMOS晶体管首先响应于从复位信号产生电路提供的复位信号导通，然后由NMOS晶体管将电容器的连接节点复位到电源电压。 然后启动升压操作，从输出端输出升压电压。

公开(公告)号：US06650570B2

公开(公告)日：2003-11-18

申请号：US09953227

申请日：2001-09-17

申请人： Toru Tanzawa ,  Shigeru Atsumi

发明人： Toru Tanzawa ,  Shigeru Atsumi

IPC分类号： G11C1604

CPC分类号： G11C11/5635 ,  G11C7/06 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/344 ,  G11C2211/5641 ,  G11C2211/565

摘要： A non-volatile semiconductor memory comprises a memory cell array having a plurality of non-volatile memory cells, at least one reference cell, a read circuit for reading data by applying a first voltage to one of word lines to compare a current flowing through one of bit lines with a current flowing through the reference cell, an erase circuit for erasing the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells, first and second regulators, and an erase verify circuit for detecting whether the erase has finished by applying an output voltage of the first regulator to word lines of the memory cells to be erased, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.