公开(公告)号：US5296729A

公开(公告)日：1994-03-22

申请号：US782623

申请日：1991-10-25

申请人： Toshiaki Yamanaka ,  Norio Hasegawa ,  Toshihiko Tanaka ,  Takashi Hashimoto ,  Koichiro Ishibashi ,  Naotaka Hashimoto ,  Akihiro Shimizu ,  Yasuhiro Sugawara ,  Tokuo Kure ,  Shimpei Iijima ,  Takashi Nishida ,  Eiji Takeda

发明人： Toshiaki Yamanaka ,  Norio Hasegawa ,  Toshihiko Tanaka ,  Takashi Hashimoto ,  Koichiro Ishibashi ,  Naotaka Hashimoto ,  Akihiro Shimizu ,  Yasuhiro Sugawara ,  Tokuo Kure ,  Shimpei Iijima ,  Takashi Nishida ,  Eiji Takeda

IPC分类号： G03F1/29 ,  G03F1/30 ,  G03F1/68 ,  H01L21/027 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/02 ,  H01L29/00 ,  H01L29/78

CPC分类号： H01L27/1108 ,  Y10S257/903

摘要： There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

摘要翻译： 提供了一种能够通过扩大连接到存储单元的标准电位电源的单元中的电极的有效面积来减小电极电阻的技术。 还提供了一种能够通过减小用于标准电位电极的电极中的电极与相邻的其它电极之间分离所需的面积来减小存储单元面积的技术。 提供了第一导电类型的两个传输MOS晶体管和两个驱动器MOS晶体管。 用于将驱动器MOS晶体管的源极电位固定为标准电位的导电层设置在传输和驱动器MOS晶体管之上，以完全覆盖存储器单元。 通过使用具有设置在相同透射部分内的光学透明基板的光掩模进行分离，其具有多个所谓的移相器区域的图案，用于反转透射相位的相位。

公开(公告)号：US5200635A

公开(公告)日：1993-04-06

申请号：US686757

申请日：1991-04-17

申请人： Toru Kaga ,  Shinichiro Kimura ,  Katsutaka Kimura ,  Yoshinobu Nakagome ,  Digh Hisamoto ,  Yoshifumi Kawamoto ,  Eiji Takeda ,  Shimpei Iijima ,  Tokuo Kure ,  Takashi Nishida

发明人： Toru Kaga ,  Shinichiro Kimura ,  Katsutaka Kimura ,  Yoshinobu Nakagome ,  Digh Hisamoto ,  Yoshifumi Kawamoto ,  Eiji Takeda ,  Shimpei Iijima ,  Tokuo Kure ,  Takashi Nishida

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/456 ,  H01L2924/0002

摘要： The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.

摘要翻译： 本发明涉及具有低电阻率布线结构的半导体器件。 直接形成在山谷和山谷结构上的布线导致薄的部分，并且在极端情况下是断开的部分。 这增加了山丘和山谷结构上的布线电阻率，降低了连接的可靠性。 在布线是存储器的数据线的情况下，随着有效长度的增加，数据线的电阻和寄生电容更大。 上述问题已经通过包括至少两层导电膜的布线来解决，所述导电膜包括作为下层的第一导电膜和作为上层的第二导电膜，并且第一导电层具有调节或平坦化山丘的表面 和底层材料中的山谷。

公开(公告)号：US5053849A

公开(公告)日：1991-10-01

申请号：US515659

申请日：1990-04-25

申请人： Ryuichi Izawa ,  Tokuo Kure ,  Shimpei Iijima ,  Eiji Takeda ,  Yasuo Igura ,  Akemi Hamada ,  Atsushi Hiraiwa

发明人： Ryuichi Izawa ,  Tokuo Kure ,  Shimpei Iijima ,  Eiji Takeda ,  Yasuo Igura ,  Akemi Hamada ,  Atsushi Hiraiwa

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/6659 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4925

摘要： Herein disclosed is a semiconductor device of high density. The semiconductor device having a high density and a microstructure is required to have a high breakdown voltage and a high speed even with a low supply voltage. The semiconductor device comprises: a semiconductor body; a gate insulating film formed over the body; and a MOS transistor having a source/drain region formed in the body and a gate electrode film formed over the gate insulating film. The gate electrode film is composed of two or more films having different etching rates. The gate etching is stopped at the interface of the composite film to form an inverse-T gate electrode structure; and in that an electric conduction is observed between the component films. Thus, the overlap between the gate and the drain can be controlled.

摘要翻译： 这里公开的是高密度的半导体器件。 具有高密度和微结构的半导体器件即使在低电源电压下也需要具有高击穿电压和高速度。 半导体器件包括：半导体本体; 形成在主体上的栅极绝缘膜; 以及形成在体内的源极/漏极区域和形成在栅极绝缘膜上的栅电极膜的MOS晶体管。 栅极电极膜由具有不同蚀刻速率的两个或更多个膜组成。 栅极蚀刻停止在复合膜的界面处以形成反T栅电极结构; 并且在组件膜之间观察到导电。 因此，可以控制栅极和漏极之间的重叠。

公开(公告)号：US5227329A

公开(公告)日：1993-07-13

申请号：US753650

申请日：1991-08-30

申请人： Takashi Kobayashi ,  Shimpei Iijima ,  Atsushi Hiraiwa ,  Nobuyoshi Kobayashi ,  Takashi Hashimoto ,  Mitsuo Nanba

发明人： Takashi Kobayashi ,  Shimpei Iijima ,  Atsushi Hiraiwa ,  Nobuyoshi Kobayashi ,  Takashi Hashimoto ,  Mitsuo Nanba

IPC分类号： H01L21/205 ,  H01L21/225 ,  H01L21/285 ,  H01L21/331 ,  H01L21/336 ,  H01L21/768 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45

CPC分类号： H01L29/66287 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2257 ,  H01L21/28525 ,  H01L21/76877 ,  H01L29/0804 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/66575 ,  H01L29/66757 ,  Y10S148/144

摘要： A boron doped amorphous silicon film is formed by CVD under the conditions of a pressure lower than 1 atm and a temperature higher than 200.degree. C. and lower than 400.degree. C. by using at least one of disilane and trisilane, and diborane as source gases. Since the resultant amorphous silicon film can diffuse impurities at a lower temperature than in the case of the polycrystalline silicon film formed by the conventional method, a pn junction much shallower than in the prior art can be formed.

摘要翻译： 通过使用乙硅烷和丙硅烷中的至少一种，乙硼烷作为源，通过CVD在低于1atm的压力和高于200℃，低于400℃的温度的条件下形成硼掺杂的非晶硅膜 气体。 由于所得到的非晶硅膜可以在比通过常规方法形成的多晶硅膜的情况下更低的温度下扩散杂质，所以可以形成比现有技术浅得多的pn结。

公开(公告)号：US6096597A

公开(公告)日：2000-08-01

申请号：US14204

申请日：1998-01-28

申请人： Robert Tsu ,  William R. McKee ,  Shimpei Iijima ,  Isamu Asano ,  Masato Kunitomo ,  Tsuyoshi Tamaru

发明人： Robert Tsu ,  William R. McKee ,  Shimpei Iijima ,  Isamu Asano ,  Masato Kunitomo ,  Tsuyoshi Tamaru

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/314 ,  H01L27/108

CPC分类号： H01L28/40 ,  H01L28/55 ,  H01L28/82

摘要： In one embodiment, the present invention provides a method of treating a dielectric layer 24. First, the dielectric layer is heated while being subjected to an O.sub.2 plasma. After that, the dielectric layer is heated while being subject to an ozone environment. This method can be useful in forming a capacitor 12 dielectric 24. In turn, the capacitor could be used in a DRAM memory device.

摘要翻译： 在一个实施例中，本发明提供了一种处理电介质层24的方法。首先，在进行O 2等离子体的同时加热电介质层。 之后，在受到臭氧环境的影响的同时加热电介质层。 该方法可用于形成电容器12电介质24.然后，电容器可用于DRAM存储器件。

公开(公告)号：US5177773A

公开(公告)日：1993-01-05

申请号：US674406

申请日：1991-03-25

申请人： Hiroaki Oizumi ,  Kozo Mochiji ,  Shimpei Iijima

发明人： Hiroaki Oizumi ,  Kozo Mochiji ,  Shimpei Iijima

IPC分类号： G03F1/22

CPC分类号： G03F1/22

摘要： An X-ray mask comprises an absorber pattern composed of a material capable of absorbing X-ray, a mask substrate for supporting the absorber pattern, composed of a material capable of transmitting X-ray, and a support frame for supporting the mask substrate, wherein the mask substrate is composed of a mask substrate material whose impurity content is suppressed to reduce positional distortions generated by X-ray radiation. Generation of positional distortions by X-ray exposure is inhibited and an arrangement of mask pattern can be ensured with a high precision.

摘要翻译： X射线掩模包括由能够吸收X射线的材料构成的吸收体图案，由能够透射X射线的材料构成的用于支撑吸收体图案的掩模基板和支撑掩模基板的支撑框架， 其特征在于，所述掩模基板由掩模基板材料构成，所述掩模基板材料的杂质含量被抑制以减少由X射线辐射产生的位置变形。 通过X射线曝光产生位置失真，可以高精度地确保掩模图案的配置。