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    Semiconductor memory device having flip-flop circuits
    2.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US5132771A

    公开(公告)日：1992-07-21

    申请号：US503928

    申请日：1990-04-04

    申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    IPC分类号： G11C11/412 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

    摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。

    Semiconductor integrated circuit device in which kink current disturbances of MOS transistors are suppressed
    4.
    发明授权
    Semiconductor integrated circuit device in which kink current disturbances of MOS transistors are suppressed 失效
    其中抑制了MOS晶体管的扭矩电流干扰的半导体集成电路器件

    公开(公告)号：US5455438A

    公开(公告)日：1995-10-03

    申请号：US69572

    申请日：1993-06-01

    申请人： Naotaka Hashimoto ,  Toshiaki Yamanaka ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Nagatoshi Ohki ,  Hiroshi Ishida

    发明人： Naotaka Hashimoto ,  Toshiaki Yamanaka ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Nagatoshi Ohki ,  Hiroshi Ishida

    IPC分类号： H01L21/762 ,  H01L27/105 ,  H01L27/088

    CPC分类号： H01L21/76237 ,  H01L27/105 ,  Y10S257/903

    摘要： Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transistors without reducing the junction characteristic of the diffusion layers and its fabrication method. In this device, an angle between the lower surface of each edge of a field oxide formed in an environmental device area, i.e. a peripheral circuit area, and the main surface of a semiconductor substrate is smaller than an angle between the lower surface of each edge of a field oxide formed in a memory cell area and the main surface of the semiconductor substrate. Further, the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the environmental device area is larger than the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the memory cell area.

    摘要翻译： 公开了一种具有多个精细存储器件及其制造方法的半导体集成电路器件，特别涉及能够抑制MOS晶体管的扭结电流干扰而不降低扩散层的结特性的半导体集成电路器件及其制造方法 。 在该装置中，形成在环境装置区域即外围电路区域的场氧化物的每个边缘的下表面与半导体衬底的主表面之间的角度小于每个边缘的下表面之间的角度 形成在存储单元区域中的场氧化物和半导体衬底的主表面。 此外，环境装置区域中的场氧化物的每个边缘在平行于半导体基板的主表面的方向上的延伸大于在平行于主体表面的方向上的延伸 半导体衬底，在存储单元区域中的场氧化物的每个边缘。

    Semiconductor memory devices having stacked polycrystalline silicon transistors
    5.
    发明授权
    Semiconductor memory devices having stacked polycrystalline silicon transistors 失效
    具有堆叠多晶硅晶体管的半导体存储器件

    公开(公告)号：US5034797A

    公开(公告)日：1991-07-23

    申请号：US497182

    申请日：1990-03-22

    申请人： Toshiaki Yamanaka ,  Yoshio Sakai ,  Takashi Hashimoto ,  Takashi Nishida ,  Satoshi Meguro ,  Shuji Ikeda ,  Eiji Takeda

    发明人： Toshiaki Yamanaka ,  Yoshio Sakai ,  Takashi Hashimoto ,  Takashi Nishida ,  Satoshi Meguro ,  Shuji Ikeda ,  Eiji Takeda

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/904

    摘要： A semiconductor device having a CMIS structure for forming a static random access memory is disclosed which device can increase the packing density of the memory and reduce the stand-by power thereof. In this semiconductor device, a first MISFET of a first conductivity type is formed on and a substrate, a second MISFET of a second conductivity type is formed over the first MISFET with a first insulating film therebetween to form a stacked CMIS structure. The second MISFET is made up of a first conductive film, a second insulating film and a second conductive film, with the source, drain and channel regions of the second MISFET being formed in the first conductive film. A first resistive drain region is formed between the channel and drain regions of the first conductive film so that an impurity of the second conductivity type is contained in the first resistive drain region at a lower concentration than in the drain region, or the first resistive drain region is substantially undoped. The first resistive drain region is disposed over the gate electrode of the first MISFET, and the gate insulating film and gate electrode of the second MISFET are formed of the second insulating film and the second conductive film, respectively. In a case where a semiconductor memory device having a static random access memory cell which is provided with a flip-flop circuit of the stacked CMIS type, is formed, a pair of first MISFET's and a pair of third MISFET's of the first conductivity type are formed on the substrate, and the second MISFET is formed on one MISFET of the first MISFET's and the third MISFET's.

    摘要翻译： 公开了具有用于形成静态随机存取存储器的CMIS结构的半导体器件，其可以增加存储器的堆积密度并降低其待机功率。 在该半导体器件中，在基板上形成第一导电型的第一MISFET，在第一MISFET上形成第二导电类型的第二MISFET，其间具有第一绝缘膜，以形成层叠的CMIS结构。 第二MISFET由第一导电膜，第二绝缘膜和第二导电膜构成，第二MISFET的源极，漏极和沟道区形成在第一导电膜中。 在第一导电膜的沟道和漏极区之间形成第一电阻漏极区，使得第一导电类型的杂质以比漏极区域低的浓度包含在第一电阻漏极区域中，或者第一电阻漏极 区域基本上未掺杂。 第一电阻漏极区域设置在第一MISFET的栅电极之上，并且第二MISFET的栅极绝缘膜和栅极电极分别由第二绝缘膜和第二导电膜形成。 在具有设置有层叠CMIS型触发电路的静态随机存取存储单元的半导体存储器件的情况下，形成一对第一MISFET和第一导电类型的一对第三MISFET 并且第一MISFET形成在第一MISFET和第三MISFET的一个MISFET上。

    SRAM having load transistor formed above driver transistor
    6.
    发明授权
    SRAM having load transistor formed above driver transistor 失效
    具有形成在驱动晶体管上方的负载晶体管的SRAM

    公开(公告)号：US5834851A

    公开(公告)日：1998-11-10

    申请号：US460641

    申请日：1995-06-02

    申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

    发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

    IPC分类号： H01L27/11

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

    摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。