-
公开(公告)号：US5296729A
公开(公告)日：1994-03-22
申请号：US782623
申请日：1991-10-25
申请人： Toshiaki Yamanaka , Norio Hasegawa , Toshihiko Tanaka , Takashi Hashimoto , Koichiro Ishibashi , Naotaka Hashimoto , Akihiro Shimizu , Yasuhiro Sugawara , Tokuo Kure , Shimpei Iijima , Takashi Nishida , Eiji Takeda
发明人： Toshiaki Yamanaka , Norio Hasegawa , Toshihiko Tanaka , Takashi Hashimoto , Koichiro Ishibashi , Naotaka Hashimoto , Akihiro Shimizu , Yasuhiro Sugawara , Tokuo Kure , Shimpei Iijima , Takashi Nishida , Eiji Takeda
IPC分类号： G03F1/29 , G03F1/30 , G03F1/68 , H01L21/027 , H01L21/8244 , H01L27/11 , H01L27/02 , H01L29/00 , H01L29/78
CPC分类号： H01L27/1108 , Y10S257/903
摘要： There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.
摘要翻译： 提供了一种能够通过扩大连接到存储单元的标准电位电源的单元中的电极的有效面积来减小电极电阻的技术。 还提供了一种能够通过减小用于标准电位电极的电极中的电极与相邻的其它电极之间分离所需的面积来减小存储单元面积的技术。 提供了第一导电类型的两个传输MOS晶体管和两个驱动器MOS晶体管。 用于将驱动器MOS晶体管的源极电位固定为标准电位的导电层设置在传输和驱动器MOS晶体管之上，以完全覆盖存储器单元。 通过使用具有设置在相同透射部分内的光学透明基板的光掩模进行分离，其具有多个所谓的移相器区域的图案，用于反转透射相位的相位。
-
公开(公告)号：USRE38296E1
公开(公告)日：2003-11-04
申请号：US08408788
申请日：1995-03-23
申请人： Noboru Moriuchi , Yoshiki Yamaguchi , Toshihiko Tanaka , Norio Hasegawa , Yoshifumi Kawamoto , Shin-ichiro Kimura , Toru Kaga , Tokuo Kure
发明人： Noboru Moriuchi , Yoshiki Yamaguchi , Toshihiko Tanaka , Norio Hasegawa , Yoshifumi Kawamoto , Shin-ichiro Kimura , Toru Kaga , Tokuo Kure
IPC分类号： H01L27108
CPC分类号： H01L27/10808 , H01L27/105 , H01L27/10852
摘要： A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.
-
公开(公告)号：US5196910A
公开(公告)日：1993-03-23
申请号：US650999
申请日：1991-02-04
申请人： Noboru Moriuchi , Yoshiki Yamaguchi , Toshihiko Tanaka , Norio Hasegawa , Yoshifumi Kawamoto , Shin-ichiro Kimura , Toru Kaga , Tokuo Kure
发明人： Noboru Moriuchi , Yoshiki Yamaguchi , Toshihiko Tanaka , Norio Hasegawa , Yoshifumi Kawamoto , Shin-ichiro Kimura , Toru Kaga , Tokuo Kure
IPC分类号： H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/105
摘要： A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.
摘要翻译： 一种半导体存储器，其中具有多个存储单元的存储单元区域和半导体衬底的表面上方相对高的高度形成在具有凹部和突出部分的半导体衬底的凹部中，并且其中外围电路区域 在半导体衬底的突出部分处形成从半导体衬底的表面相对较低的高度。
-
4.发明授权
公开(公告)号：US4882289A
公开(公告)日：1989-11-21
申请号：US184786
申请日：1988-04-22
申请人： Noboru Moriuchi , Yoshiki Yamaguchi , Toshihiko Tanaka , Norio Hasegawa , Yoshifumi Kawamoto , Shin-ichiro Kimura , Toru Kaga , Tokuo Kure
发明人： Noboru Moriuchi , Yoshiki Yamaguchi , Toshihiko Tanaka , Norio Hasegawa , Yoshifumi Kawamoto , Shin-ichiro Kimura , Toru Kaga , Tokuo Kure
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/105 , Y10S438/911
摘要： A semiconductor memory wherein a memory cell region having a plurality of memory cells and has higher altitude from the surface of semiconductor substrate is formed in the recessed part of semiconductor substrate having the recessed part and projected part and a peripheral circuit region which is comparatively low from the surface of semiconductor substrate is formed to the projected part of semiconductor substrate.
摘要翻译： 一种半导体存储器，其中具有多个存储单元并且具有来自半导体衬底的表面的较高高度的存储单元区域形成在具有凹陷部分和突起部分的半导体衬底的凹部中，并且外围电路区域相对较低 半导体衬底的表面形成在半导体衬底的突出部分上。
-
公开(公告)号：US5328807A
公开(公告)日：1994-07-12
申请号：US711954
申请日：1991-06-07
申请人： Toshihiko Tanaka , Norio Hasegawa , Toshiaki Yamanaka , Akira Imai , Hiroshi Shiraishi , Takumi Ueno , Hiroshi Fukuda
发明人： Toshihiko Tanaka , Norio Hasegawa , Toshiaki Yamanaka , Akira Imai , Hiroshi Shiraishi , Takumi Ueno , Hiroshi Fukuda
CPC分类号： G03F1/34 , G03F7/2022
摘要： A comb-like or dot-like phase shifter pattern is added to a phase shifter used in phase shifting mask technology, which is then exposed onto a wafer. This enables the formation of extremely fine line patterns or space patterns having widths different from each other simultaneously. Further, when two reticles are disposed such that phase shifter patterns disposed therein intersect each other and are exposed consecutively onto a wafer, a fine hole pattern or dot pattern can be formed at a position where the phase shifter patterns intersect each other.
摘要翻译： 将梳状或点状移相器图案添加到用于相移掩模技术的移相器中，然后将其暴露在晶片上。 这使得能够同时形成彼此宽度不同的极细线图案或空间图案。 此外，当两个掩模版被布置成使得设置在其中的移相器图案彼此相交并且连续地暴露在晶片上时，可以在移相器图案彼此相交的位置处形成细孔图案或点图案。
-
公开(公告)号：US20060273405A1
公开(公告)日：2006-12-07
申请号：US11504738
申请日：2006-08-16
CPC分类号： H01L27/10882 , G03F1/36 , H01L21/32139 , H01L23/528 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.
-
7.发明授权Semiconductor device and method for patterning the semiconductor device in which line patterns terminate at different lengths to prevent the occurrence of a short or break 有权图案化半导体器件的半导体器件和方法，其中线图案以不同长度终止以防止发生短路或断线公开(公告)号：US06495870B1
公开(公告)日：2002-12-17
申请号：US09342239
申请日：1999-06-29
IPC分类号： H01L2710
CPC分类号： H01L27/10882 , G03F1/36 , H01L21/32139 , H01L23/528 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.
摘要翻译： 在用于构图字和数据线的掩模图案（a）中，在相邻字线之间改变长度以便在其尖端处彼此偏移，此外，每个字线的尖端被倾斜地切割。因此可能 以防止抗蚀剂图案与相邻图案分离和接触。 因此，也可以防止图案线的断裂故障和这些图案线之间的短路故障。
-
公开(公告)号：US07105873B2
公开(公告)日：2006-09-12
申请号：US10282044
申请日：2002-10-29
IPC分类号： H01L27/10
CPC分类号： H01L27/10882 , G03F1/36 , H01L21/32139 , H01L23/528 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely.It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.
-
公开(公告)号：US07582921B2
公开(公告)日：2009-09-01
申请号：US11504738
申请日：2006-08-16
IPC分类号： H01L27/10
CPC分类号： H01L27/10882 , G03F1/36 , H01L21/32139 , H01L23/528 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.
摘要翻译： 在用于构图字和数据线的掩模图案（a）中，在相邻字线之间改变长度以便在其尖端处彼此偏移，此外，每个字线的尖端被倾斜地切割。 因此可以防止抗蚀剂图案与相邻图案分离和接触。 因此，也可以防止图案线的断裂故障和这些图案线之间的短路故障。
-
公开(公告)号：US06936406B2
公开(公告)日：2005-08-30
申请号：US10364702
申请日：2003-02-12
申请人： Norio Hasegawa , Joji Okada , Toshihiko Tanaka , Kazutaka Mori , Ko Miyazaki
发明人： Norio Hasegawa , Joji Okada , Toshihiko Tanaka , Kazutaka Mori , Ko Miyazaki
CPC分类号： G03F1/56 , G03F1/70 , G03F7/0035 , G03F7/70433 , G03F7/707 , H01L21/0274 , Y10S438/942 , Y10S438/945 , Y10S438/948 , Y10S438/95
摘要： In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.
-
-
-
-
-
-
-
-
-
搜索结果
191 条记录 (耗时 0.055 秒)
