公开(公告)号：US20190393114A1

公开(公告)日：2019-12-26

申请号：US16267888

申请日：2019-02-05

Applicant: Toshiba Memory Corporation

Inventor： Satoshi TSUKIYAMA ,  Hideo AOKI ,  Masatoshi KAWATO ,  Masayuki MIURA ,  Masatoshi FUKUDA ,  Soichi HOMMA

IPC: H01L23/31 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/29 ,  H01L21/56

Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.

公开(公告)号：US20180261574A1

公开(公告)日：2018-09-13

申请号：US15694838

申请日：2017-09-03

Applicant: Toshiba Memory Corporation

Inventor： Yuji KARAKANE ,  Masatoshi FUKUDA ,  Soichi HOMMA ,  Masayuki MIURA ,  Naoyuki KOMUTA ,  Yuka AKAHANE ,  Yukifumi OYAMA

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/29 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/76897 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1415 ,  H01L2224/1416 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81065 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/1438 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.

公开(公告)号：US20180076187A1

公开(公告)日：2018-03-15

申请号：US15445988

申请日：2017-03-01

Applicant: Toshiba Memory Corporation

Inventor： Yuji KARAKANE ,  Masatoshi FUKUDA ,  Soichi HOMMA ,  Naoyuki KOMUTA ,  Yukifumi OYAMA

IPC: H01L25/00 ,  H01L21/56 ,  H01L25/18 ,  H01L21/683 ,  H01L23/00

Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.

公开(公告)号：US20210242191A1

公开(公告)日：2021-08-05

申请号：US17233937

申请日：2021-04-19

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Toshihiko OHDA ,  Tetsuya KUROSAWA ,  Masatoshi FUKUDA

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065

Abstract: A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.

公开(公告)号：US20200185373A1

公开(公告)日：2020-06-11

申请号：US16793323

申请日：2020-02-18

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuji KARAKANE ,  Masatoshi FUKUDA ,  Soichi HOMMA ,  Naoyuki KOMUTA ,  Yukifumi OYAMA

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065

Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.