公开(公告)号：US20050237501A1

公开(公告)日：2005-10-27

申请号：US10829623

申请日：2004-04-22

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horal ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horal ,  Charles Koburger ,  Peter Mitchell

IPC分类号： G03B27/52 ,  G03F7/20

CPC分类号： G03F7/70341

摘要： An apparatus, system and method for use with a photolithographic system. In accordance with one embodiment, the photolithographic system of the present invention includes a workpiece support member for supporting a semiconductor wafer. A substantially transparent cover member is disposed over the workpiece support member to form a substantially enclosed workpiece cell therebetween. The enclosed workpiece cell is filled with a first immersion fluid having suitable refractive properties. The cover member, having suitable refractive properties, includes an upper surface contoured to form an open reservoir containing a second immersion fluid, having suitable refractive properties, and in which a final lens element may be immersed during a lithography process.

摘要翻译： 一种用于光刻系统的设备，系统和方法。 根据一个实施例，本发明的光刻系统包括用于支撑半导体晶片的工件支撑构件。 基本上透明的盖构件设置在工件支撑构件上方，以在它们之间形成基本封闭的工件单元。 封闭的工件单元填充有具有合适折射特性的第一浸没流体。 具有合适的折射性质的盖构件包括上表面，其形状为形成具有合适的折射性质的第二浸没流体的开口储存器，并且其中最终的透镜元件可以在光刻工艺期间被浸没。

公开(公告)号：US20070184588A1

公开(公告)日：2007-08-09

申请号：US11735075

申请日：2007-04-13

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

公开(公告)号：US20060169972A1

公开(公告)日：2006-08-03

申请号：US10906016

申请日：2005-01-31

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

IPC分类号： H01L29/06

CPC分类号： H01L27/0688 ,  B82Y10/00 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/0705 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/057 ,  Y10S977/938

摘要： A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor. A method of forming the inventive hybrid semiconductor structure having at least one shared node between the vertical carbon nanotube transistor and the horizontal semiconductor device is also provided.

摘要翻译： 提供一种混合半导体结构，其包括水平半导体器件和垂直碳纳米管晶体管，其中垂直碳纳米管晶体管和水平半导体器件具有至少一个共享节点。 至少一个共享节点可以包括例如FET的漏极，源极或栅极电极，或双极晶体管的发射极，集电极或基极。 还提供了形成本发明的混合半导体结构的方法，该结构在竖直碳纳米管晶体管和水平半导体器件之间具有至少一个共享节点。

公开(公告)号：US20050179029A1

公开(公告)日：2005-08-18

申请号：US10777576

申请日：2004-02-12

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： G11C13/02 ,  H01L21/336 ,  H01L27/28 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L29/06

CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

摘要翻译： 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US20050167655A1

公开(公告)日：2005-08-04

申请号：US10767065

申请日：2004-01-29

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： B82B1/00 ,  B82B3/00 ,  H01L27/28 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L29/06

CPC分类号： H01L51/057 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/70 ,  Y10S977/734 ,  Y10S977/742

摘要： Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

摘要翻译： 结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。 每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。 可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。 可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

公开(公告)号：US20050087875A1

公开(公告)日：2005-04-28

申请号：US10605766

申请日：2003-10-24

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wiring-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.

摘要翻译： 在半导体器件结构上形成具有支撑结构的气体电介质的方法为半导体器件结构的导体提供低电容和足够的支撑。 在布线层电介质中形成诸如通孔或互连的导电结构。 然后形成连接到导电结构的支撑件，支撑件包括其下的区域。 然后从该区域去除布线层电介质以形成气体电介质。

公开(公告)号：US20060008927A1

公开(公告)日：2006-01-12

申请号：US11221118

申请日：2005-09-07

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

IPC分类号： H01L21/00

CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。

公开(公告)号：US20050202322A1

公开(公告)日：2005-09-15

申请号：US10798908

申请日：2004-03-11

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F9/00

CPC分类号： G03F1/30

摘要： Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

摘要翻译： 用于制造用于半导体光刻系统中的交替相移掩模或掩模版的方法。 所述方法通常包括在手柄基板上形成一层相移掩模材料，并且图案化该层以限定凹陷的相移窗口。 图案层从手柄晶片转移到掩模板。 相移窗口的深度由相移掩模材料层的厚度确定，并且与图案化工艺无关。 特别地，相移窗口的深度不依赖于通过掩模板的表面的蚀刻工艺的蚀刻速率均匀性。

公开(公告)号：US20050189655A1

公开(公告)日：2005-09-01

申请号：US10787640

申请日：2004-02-26

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48

CPC分类号： B82Y10/00 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

摘要翻译： 集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。 优选地，导电路径包括在导电层之间延伸的通孔。 优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔 有铜的腔。 然后在通孔上形成下一导电层。

公开(公告)号：US20050129948A1

公开(公告)日：2005-06-16

申请号：US10733974

申请日：2003-12-11

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Hotak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Hotak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： C01B31/02 ,  B32B9/00 ,  B82B3/00 ,  C01B31/00 ,  H01J1/304 ,  H01J9/02 ,  H01L29/04

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B2202/06 ,  C01B2202/22 ,  C01B2202/34 ,  H01J1/3044 ,  H01J2201/30469 ,  Y10S977/742 ,  Y10S977/84 ,  Y10S977/842 ,  Y10S977/843 ,  Y10T428/30

摘要： A method for synthesizing carbon nanotubes and structure formed thereby. The method includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access. As the carbon nanotubes lengthen during resumed nanotube synthesis, access to the synthesis sites remains unoccluded.

摘要翻译： 一种合成碳纳米管的方法及由此形成的结构。 该方法包括在由第一基板支撑的多个合成位置上形成碳纳米管，中断纳米管合成，将每个碳纳米管的自由端安装到第二基板上，以及去除第一基板。 每个碳纳米管被其中一个合成位点封盖，生长反应物可以随时进入。 由于碳纳米管在恢复纳米管合成过程中延长，所以进入合成位点仍未被排除。