公开(公告)号：US06233956B1

公开(公告)日：2001-05-22

申请号：US09543882

申请日：2000-04-06

申请人： Toshiharu Katayama ,  Kazuhiko Watanabe

发明人： Toshiharu Katayama ,  Kazuhiko Watanabe

IPC分类号： F25B4104

CPC分类号： F25B41/062 ,  F25B41/04 ,  F25B2341/0683

摘要： A valve body 10 of an expansion valve 1 comprises a valve chamber 14 to which refrigerant from a compressor is supplied. The amount of refrigerant is controlled between a valve member 40 and a valve seat 16, and travels through a first passage 20 to an evaporator. The refrigerant returning from the evaporator travels through a second passage 50 and into the compressor. The valve chamber 14 is equipped with a bypass passage which is communicated through a narrow hole 24 to an opening 26 with a bottom, and through a conduit 28 to the first passage 20. The electromagnetic valve 100 comprises a plunger 130, and opens/closes the bypass passage by a pilot valve 150. A pressure switch 220 is equipped to an opening 54 communicated to the second passage 50, and when the pressure of the refrigerant returning from the evaporator is reduced, the valve 100 is operated and the bypass passage is opened.

摘要翻译： 膨胀阀1的阀体10包括供给来自压缩机的制冷剂的阀腔14。 在阀构件40和阀座16之间控制制冷剂的量，并且通过第一通道20行进到蒸发器。 从蒸发器返回的制冷剂通过第二通道50进入压缩机。 阀室14配备有旁通通道，旁通通道通过窄孔24连通到具有底部的开口26，并且通过导管28连接到第一通道20.电磁阀100包括柱塞130，并且打开/关闭 通过先导阀150的旁通通路。压力开关220配备到与第二通路50连通的开口54，并且当从蒸发器返回的制冷剂的压力减小时，阀100被操作，旁通通道 开了

公开(公告)号：US5850149A

公开(公告)日：1998-12-15

申请号：US755616

申请日：1996-11-25

申请人： Toshiharu Katayama ,  Naoko Ohtani ,  Yukari Imai

发明人： Toshiharu Katayama ,  Naoko Ohtani ,  Yukari Imai

IPC分类号： H01L21/3063 ,  H01L21/66 ,  H01L29/78 ,  G01R31/26 ,  C23F1/14

CPC分类号： H01L22/24 ,  H01L22/20

摘要： A part of a gate insulation film between a semiconductor substrate and an exposed gate electrode of a semiconductor device is partially and stepwise etched away. A voltage is applied between the semiconductor substrate and the gate electrode in a chemical wet etching system at each step. An anode oxide film is formed on the surface of the gate electrode in a step, when a defect is included in a gate oxide film. The gate electrode is etched away in another step, when a defect is not included in the gate oxide film. A position of a defect in the gate insulation film is detected from the difference in the area of the gate insulation film when an anode oxide film is formed on the gate electrode, and when the gate electrode is etched away.

摘要翻译： 在半导体衬底和半导体器件的暴露的栅电极之间的栅极绝缘膜的一部分被部分和逐步蚀刻掉。 在每个步骤中，在化学湿蚀刻系统中，在半导体衬底和栅电极之间施加电压。 当在栅极氧化膜中包含缺陷时，在栅电极的表面上形成阳极氧化膜。 当栅极氧化膜中不包括缺陷时，在另一步骤中蚀刻掉栅电极。 当在栅电极上形成阳极氧化膜时，以及当栅电极被蚀刻掉时，从栅极绝缘膜的面积的差异来检测栅极绝缘膜中的缺陷的位置。

公开(公告)号：US20080251742A1

公开(公告)日：2008-10-16

申请号：US11884863

申请日：2006-02-24

申请人： Sadatake Ise ,  Shu Yanagisawa ,  Masaki Tomaru ,  Toshiharu Katayama

发明人： Sadatake Ise ,  Shu Yanagisawa ,  Masaki Tomaru ,  Toshiharu Katayama

IPC分类号： F16K31/00 ,  F16K31/126 ,  F25B41/00 ,  F25B41/04

CPC分类号： F25B41/062 ,  F25B40/00 ,  F25B2309/061 ,  F25B2341/063 ,  F25B2341/0683 ,  F25B2500/01

摘要： There is disclosed a pressure control valve comprising: a valve body (10A) provided successively with, mentioning from the upstream side in the flowing direction of refrigerant, a refrigerant inflow port (11), a refrigerant introduction chamber (14), a valve seat (13) with which a rod-like valve (15) is retractably contacted, and a refrigerant outflow port (12); and a temperature-sensitive/pressure-responsive element (20) which is provided with a temperature sensitive chamber (25) for sensing the temperature of the refrigerant that has been introduced into the refrigerant introduction chamber (14) and is designed to drive the valve (15) in opening or closing direction in response to fluctuations of the inner pressure of the temperature sensitive chamber (25). The temperature-sensitive/pressure-responsive element (20) is integrally attached to the valve body (10A).

摘要翻译： 公开了一种压力控制阀，包括：阀体（10A），从制冷剂的流动方向的上游侧，制冷剂流入口（11），制冷剂导入室（14），阀 座杆（13）与杆状阀（15）可伸缩地接触，以及制冷剂流出口（12）。 和温度敏感/压力响应元件（20），其设置有用于感测已经被引入制冷剂引入室（14）的制冷剂的温度的温度敏感室（25），并被设计成驱动阀 （15）响应于所述感温室（25）的内部压力的波动而处于打开或关闭方向。 温度敏感/压力响应元件（20）一体地附接到阀体（10A）。

公开(公告)号：US5786612A

公开(公告)日：1998-07-28

申请号：US633093

申请日：1996-04-16

申请人： Naoko Otani ,  Toshiharu Katayama

发明人： Naoko Otani ,  Toshiharu Katayama

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L27/115

摘要： Each of source regions (4) is provided only immediately below a bottom surface (3B) of each of trenches (3) which is formed in a silicon substrate (1), extending inward from a main surface (1S) thereof along a second direction, and each of gate electrode portions (23) is provided inside each of the trenches (3). Specifically, each of the gate electrode portions (23) consists of a gate oxide film (19) formed on a side surface (S1) and part of the bottom surface (3B) of the trench (3), an FG electrode (20) formed thereon, a gate insulating film (21) formed on a side surface of the FG electrode (20) which is out of contact with the gate oxide film (19), an upper surface of the FG electrode (20), a side surface (2S) and the other part of the bottom (3B) of the trench (3), and a CG electrode (22) formed so as to cover an upper surface of the gate insulating film (21). Each of drain regions (11) is shared by the two adjacent transistors. The device configuration as above achieves reduction in area of the gate electrode portions (23) and further reduction in each level difference between both regions having and not having the gate electrode portion (23). Thus, reduction in level difference of each memory cell is achieved while reduction in area of each memory cell is ensured.

摘要翻译： 每个源极区域（4）仅设置在形成在硅衬底（1）中的每个沟槽（3）的底表面（3B）的正下方，从其主表面（1S）向内沿着第二方向 并且每个沟槽（3）内设置有栅电极部（23）。 具体而言，各栅电极部（23）由形成在沟槽（3）的侧面（S1）和底面（3B）的一部分的栅极氧化膜（19），FG电极（20） 形成在与栅极氧化膜（19）不接触的FG电极（20）的侧面上的栅极绝缘膜（21），FG电极（20）的上表面，侧面 （2S）和沟槽（3）的底部（3B）的另一部分，以及形成为覆盖栅极绝缘膜（21）的上表面的CG电极（22）。 漏极区域（11）中的每一个由两个相邻的晶体管共享。 如上所述的器件结构实现了栅电极部分（23）的面积减小，并且进一步减小了具有栅极电极部分（23）的两个区域之间的每个电平差。 因此，在确保每个存储单元的面积减小的同时，实现每个存储单元的电平差的减小。

公开(公告)号：US5708285A

公开(公告)日：1998-01-13

申请号：US526391

申请日：1995-09-11

申请人： Naoko Otani ,  Toshiharu Katayama

发明人： Naoko Otani ,  Toshiharu Katayama

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  G11C11/5621 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/7887 ,  G11C2211/5612

摘要： A non-volatile semiconductor storage device with which a multi-value memory is realized and the amount of information storable is increased without increasing the number of memory transistors and the area occupied thereby. A gate electrode portion 20a of each memory transistor has a two-layer floating gate structure comprising two floating gate electrodes 22a, 22b and a control gate electrode 24 which are substantially vertically laminated one above another. The non-volatile semiconductor storage device is thereby constructed as a multi-value memory capable of providing a state "1" where electrons are injected into the first floating gate electrode 22a, a state "0" where electrons are injected into the first and second floating gate electrodes 22a, 22b, and a state "2" where electrons are withdrawn from the first and second floating gate electrodes 22a, 22b.

摘要翻译： 实现多值存储器的非易失性半导体存储装置，并且不增加存储晶体管的数量和由此占用的面积来增加可存储的信息量。 每个存储晶体管的栅电极部分20a具有两层浮栅结构，包括两个浮置栅电极22a，22b和控制栅电极24，它们基本上垂直层叠在另一个上。 因此，非易失性半导体存储装置被构造为能够提供电子注入到第一浮栅电极22a中的状态“1”的多值存储器，其中电子注入第一和第二浮动栅电极22a的状态“0” 浮栅电极22a，22b和电子从第一和第二浮栅22a，22b取出的状态“2”。

公开(公告)号：US5677204A

公开(公告)日：1997-10-14

申请号：US630211

申请日：1996-04-10

申请人： Yukari Imai ,  Toshiharu Katayama ,  Naoko Otani

发明人： Yukari Imai ,  Toshiharu Katayama ,  Naoko Otani

IPC分类号： G01N21/88 ,  G01N21/956 ,  H01L21/3063 ,  H01L21/321 ,  H01L21/66 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  G01R31/26 ,  H01L21/306 ,  H01L21/479

CPC分类号： H01L27/1085 ,  H01L21/32105 ,  H01L21/823878 ,  H01L27/11517

摘要： A semiconductor device (100) including a silicon substrate (1), a gate oxide film (2) formed on the silicon substrate (1) and having a defect (3) and a dielectric breakdown voltage failure portion (4), and a polysilicon film (5) formed on the gate oxide film (2) is immersed in a chemical etchant (7) in a wet etching apparatus (9). With the silicon substrate (1) serving as an anode, a DC voltage source (6) of the wet etching apparatus (9) applies voltage to the silicon substrate (1) to perform anode oxidation. Passivation layers (10) are formed on parts of the surface of the polysilicon film (5) which overlies the defect (3) and dielectric breakdown voltage failure portion (4) but are not formed on the surface of the polysilicon film (5) in regions insulated by the gate oxide film (2). The polysilicon film (5) in the regions on which the passivation layers (10) are not formed is removed by the chemical etchant (7).

摘要翻译： 一种半导体器件（100），包括硅衬底（1），形成在硅衬底（1）上并具有缺陷（3）和介电击穿电压失效部分（4）的栅极氧化膜（2） 形成在栅极氧化膜（2）上的膜（5）在湿式蚀刻装置（9）中浸渍在化学蚀刻剂（7）中。 在硅衬底（1）用作阳极的情况下，湿蚀刻装置（9）的直流电压源（6）向硅衬底（1）施加电压以进行阳极氧化。 钝化层（10）形成在多晶硅膜（5）的覆盖缺陷（3）和绝缘击穿电压失效部分（4）但不形成在多晶硅膜（5）的表面上的部分上， 由栅氧化膜（2）绝缘的区域。 通过化学蚀刻剂（7）除去未形成有钝化层（10）的区域中的多晶硅膜（5）。

公开(公告)号：US06636824B1

公开(公告)日：2003-10-21

申请号：US09567029

申请日：2000-05-08

申请人： Kouetsu Sawai ,  Masahiko Ikeno ,  Toshiharu Katayama

发明人： Kouetsu Sawai ,  Masahiko Ikeno ,  Toshiharu Katayama

IPC分类号： G06F1900

CPC分类号： G01R31/307 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus for inspecting a semiconductor device comprises a wafer stage (2), a stage driving unit (3), a charged-particle beam irradiation unit (4), an electronic optical system (11), a charged-particle beam control unit (12), a secondary-electron detection unit (5), an amplifier (7), a secondary-electron intensity comparison unit (8), a database (9) connected to an output of the secondary-electron intensity comparison unit (8), a PC (10) connected to an output of the database (9) and a main control unit (6) connected to the output of the database (9) and an output of the PC (10), whose output is connected to the stage driving unit (3), the charged-particle beam irradiation unit (4) and the charged-particle beam control unit (12). The database (9) stores inspection results and inspection addresses on m inspection regions (15) with strong possibility of having opening failures of contact holes (16) in each of a plurality of semiconductor wafers (1).

摘要翻译： 用于检查半导体器件的装置包括晶片台（2），平台驱动单元（3），带电粒子束照射单元（4），电子光学系统（11），带电粒子束控制单元 12），二次电子检测单元（5），放大器（7），二次电子强度比较单元（8），连接到二次电子强度比较单元（8）的输出端的数据库（9） ，连接到数据库（9）的输出的PC（10）和连接到数据库（9）的输出的主控制单元（6）和PC（10）的输出，其输出连接到 带电粒子束照射单元（4）和带电粒子束控制单元（12）。 数据库（9）存储在多个半导体晶片（1）的每一个中具有接触孔（16）的打开故障的可能性很大的m个检查区域（15）的检查结果和检查地址。

公开(公告)号：US5705027A

公开(公告)日：1998-01-06

申请号：US551597

申请日：1995-11-01

申请人： Toshiharu Katayama ,  Naoko Ootani

发明人： Toshiharu Katayama ,  Naoko Ootani

IPC分类号： H01L21/306 ,  C25F3/12 ,  H01L21/3063

CPC分类号： C25F3/12 ,  H01L21/3063 ,  Y10S438/911

摘要： The method is to selectively etch the etching residue in non-conductive state occurring in semiconductor manufacturing process. A silicon substrate cassette is used in such selective etching. In removing the etching residue in non-conductive state occurring in semiconductor manufacturing process, by applying a positive potential to part of conductive silicon substrates in an etching solution, the contact surfaces between the silicon substrates and the portion electrically connected thereto and the chemical etching solution are anodically oxidized to protect with a passive film, while only the etching residue in non-conductive state is selectively removed by isotropic etching, thereby achieving the purpose.

摘要翻译： 该方法是选择性地蚀刻在半导体制造工艺中出现的非导电状态的蚀刻残留物。 在这种选择性蚀刻中使用硅衬底盒。 在去除在半导体制造工艺中出现的非导电状态的蚀刻残留物中，通过在蚀刻溶液中对部分导电硅衬底施加正电位，硅衬底与电连接的部分和化学蚀刻溶液之间的接触表面 被阳极氧化以用钝化膜保护，而仅通过各向同性蚀刻选择性地去除非导电状态的蚀刻残留物，从而实现目的。

公开(公告)号：US5047831A

公开(公告)日：1991-09-10

申请号：US444358

申请日：1989-12-01

申请人： Toshiharu Katayama

发明人： Toshiharu Katayama

IPC分类号： H01L21/302 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/36 ,  H01L29/417

CPC分类号： H01L29/66636 ,  H01L21/28512 ,  H01L29/36 ,  H01L29/41766

摘要： A semiconductor device comprising a contact region having reduced contact resistance is provided by the steps of implanting ions of impurities to a predetermined region of a main surface of a semiconductor substrate; forming an impurity diffusion region by applying heat treatment at 400.degree. C.; etching the region from the surface of the semiconductor substrate to the maximum point of an ion concentration to form a metal wiring layer on the exposed surface of the thus formed impurity diffusion region. Since the impurity diffusion region is connected to the metal wiring layer at the maximum point of the ion concentration, the contact resistance can be a low value.

摘要翻译： 包括具有降低的接触电阻的接触区域的半导体器件通过以下步骤提供：将杂质离子注入半导体衬底的主表面的预定区域; 通过在400℃下进行热处理形成杂质扩散区; 将该区域从半导体衬底的表面蚀刻到离子浓度的最大点，以在由此形成的杂质扩散区域的暴露表面上形成金属布线层。 由于杂质扩散区域在离子浓度的最大点与金属布线层连接，所以接触电阻可以是低值。

公开(公告)号：US07023541B2

公开(公告)日：2006-04-04

申请号：US10386558

申请日：2003-03-13

申请人： Mariko Mizuo ,  Toshiharu Katayama

发明人： Mariko Mizuo ,  Toshiharu Katayama

IPC分类号： G01N21/00

CPC分类号： G01N21/95607 ,  G01N21/9501 ,  G01N2021/95615

摘要： An inspection device inspecting for a defect of a semiconductor wafer based on an image of the wafer surface includes an imaging device obtaining image data of a wafer subjected to inspection, a storage circuit storing reference image data of the wafer, an image comparison unit comparing the image data of the wafer subjected to inspection and the reference image data using an inspection condition, an acquiring circuit acquiring wafer in process (WIP) data of the wafer subjected to inspection, and a WIP data operating unit setting the inspection condition based on the WIP data obtained.

摘要翻译： 基于晶片表面的图像检查半导体晶片的缺陷的检查装置包括：获得检查的晶片的图像数据的成像装置，存储晶片的参考图像数据的存储电路;图像比较单元， 使用检查条件的晶片的图像数据和使用检查条件的参考图像数据，获取电路获取经过检查的晶片的处理（WIP）数据的晶片;以及WIP数据操作单元，其基于WIP设定检查条件 获得的数据。