公开(公告)号：US06198686B1

公开(公告)日：2001-03-06

申请号：US09613583

申请日：2000-07-10

申请人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

发明人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087

摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of-an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

摘要翻译： 一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。 另一方面，响应于发出激活命令，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少 定时裕度，经由延迟电路20A到预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。 每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号 字解码器中的锁存电路。

公开(公告)号：US6111795A

公开(公告)日：2000-08-29

申请号：US342059

申请日：1999-06-29

申请人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

发明人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C11/4076 ,  G11C11/4087 ,  G11C8/10 ,  G11C8/18

摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

摘要翻译： 一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。 另一方面，响应于激活命令的发出，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少定时 通过延迟电路20A将预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。 每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号 字解码器中的锁存电路。

公开(公告)号：US06317353B1

公开(公告)日：2001-11-13

申请号：US09536449

申请日：2000-03-28

申请人： Toshimi Ikeda ,  Masato Matsumiya ,  Masato Takita

发明人： Toshimi Ikeda ,  Masato Matsumiya ,  Masato Takita

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C5/14

摘要： A power supply line is formed over a memory cell array which has arranged a plurality of memory cells using a metal wiring layer M1 which is disposed on the side closest to the memory cell array, of all the metal wiring layers. The power supply lines are formed over the memory cell array using not only an upper metal wiring layer M2 but the metal wiring layer M1 so that the wiring resistance of the power supply lines may decrease and a sufficient amount of current can be supplied to the power supply lines. Consequently, the circuits supplied with an electric current through the power supply lines become capable of high-speed operation. This is particularly effective for the high-speed operation of the circuits arranged around the memory cell array. The power supply line formed using the lower metal wiring layer M1 is connected over the memory cell array to a power supply line which is formed using the metal wiring layer M2 on the upper layer than the metal wiring layer M1. Therefore, the netlike configuration of the power supply lines can be made with higher density compared to conventional ones.

摘要翻译： 电源线形成在存储单元阵列上，该存储单元阵列使用布置在最靠近存储单元阵列的一侧的金属布线层M1布置了多个存储单元。 电源线不仅使用上金属布线层M2而且金属布线层M1形成在存储单元阵列的上方，使得电源线的布线电阻可能降低，并且能够向电源提供足够的电流量 供应线。 因此，通过电源线提供电流的电路变得能够高速运行。 这对于布置在存储单元阵列周围的电路的高速操作特别有效。 使用下金属布线层M1形成的电源线通过存储单元阵列连接到使用上层的金属布线层M2形成的电源线，而不是金属布线层M1。 因此，与常规电源线相比，可以以更高的密度制造电源线的网状结构。

公开(公告)号：US06522003B1

公开(公告)日：2003-02-18

申请号：US09472833

申请日：1999-12-28

申请人： Takayoshi Minami ,  Osamu Tsuboi ,  Toshimi Ikeda ,  Masato Matsumiya ,  Kuninori Kawabata

发明人： Takayoshi Minami ,  Osamu Tsuboi ,  Toshimi Ikeda ,  Masato Matsumiya ,  Kuninori Kawabata

IPC分类号： H01L2348

CPC分类号： G03F7/70633 ,  G03F9/7084 ,  H01L23/522 ,  H01L23/544 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device characterized by comprising a first insulating film formed on the semiconductor substrate, a first wiring or mark formed on the first insulating film, an electrically isolated pattern formed under the first insulating film and below the first wiring or mark, a hole formed in the first insulating film to connect the first wiring or mark and the electrically isolated pattern, and a second insulating film for covering the first wiring or mark.

摘要翻译： 一种半导体器件，其特征在于，包括形成在所述半导体衬底上的第一绝缘膜，形成在所述第一绝缘膜上的第一布线或标记，形成在所述第一绝缘膜下方且在所述第一布线或标记下方的电隔离图案， 用于连接第一布线或标记和电隔离图案的第一绝缘膜，以及用于覆盖第一布线或标记的第二绝缘膜。

公开(公告)号：US5994004A

公开(公告)日：1999-11-30

申请号：US19743

申请日：1998-02-06

申请人： Yasuko Tabata ,  Satoru Asai ,  Toshimi Ikeda ,  Masato Matsumiya

发明人： Yasuko Tabata ,  Satoru Asai ,  Toshimi Ikeda ,  Masato Matsumiya

IPC分类号： G03F1/30 ,  G03F1/68 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F1/30

摘要： A photomask has a plurality of transparent regions defined in an opaque region and classified into first and second groups. Each of the transparent regions belonging to one of the first and second groups is provided with a phase shifter, so that the phase of light transmitted through the transparent region belonging to the first group becomes different from the phase of light transmitted through the transparent region belonging to the second group. The photomask includes: a pair of first transparent regions belonging to the first group and including linear portions disposed in parallel, a virtual straight line interconnecting one ends of the first transparent regions intersecting at a right angle with the extension direction of the linear portions; and a second transparent region belonging to the second group and disposed at the center between, and in parallel to, the linear portions of the pair of first transparent regions, the second transparent region including a linear thickportion and a linear thin portion, the linear thin portion being disposed in an area between the pair of first transparent regions and continuously coupled to the linear thick portion, and a connection portion between the thick and thin portions being indented from the virtual straight line toward the area between the pair of first transparent regions.

摘要翻译： 光掩模具有限定在不透明区域中并被分类为第一和第二组的多个透明区域。 属于第一组和第二组中的一个的透明区域中的每一个设置有移相器，使得透过属于第一组的透明区域的光的相位与透过透明区域的光的相位不同 到第二组。 光掩模包括：属于第一组的一对第一透明区域，并且包括平行设置的直线部分，将与直线部分的延伸方向成直角相交的第一透明区域的一端相互连接的虚拟直线; 以及属于第二组的第二透明区域，并且设置在一对第一透明区域的直线部分之间并且平行于中心，第二透明区域包括线性​​厚度部分和线状薄部分，线性薄片 部分设置在一对第一透明区域之间的区域中并且连续地连接到线状厚部分，并且厚部分和薄部分之间的连接部分从假想直线向着该对第一透明区域之间的区域缩进。

公开(公告)号：US07281155B1

公开(公告)日：2007-10-09

申请号：US09359767

申请日：1999-07-22

申请人： Satoshi Eto ,  Masato Matsumiya ,  Toshimi Ikeda ,  Yuki Ishii ,  Akira Kikutake ,  Kuninori Kawabata

发明人： Satoshi Eto ,  Masato Matsumiya ,  Toshimi Ikeda ,  Yuki Ishii ,  Akira Kikutake ,  Kuninori Kawabata

IPC分类号： H02H3/05

CPC分类号： G11C29/78

摘要： A semiconductor memory device having a shift redundancy function includes a switch circuit for changeably connecting a plurality of decode signal lines decoding an address signal to a plurality of selecting lines and redundancy selecting lines, and executes a switch operation for shifting at least one of a plurality of decode lines in the direction of a first redundancy selecting line positioned at one of the ends among a plurality of selecting lines or a second switch operation for shifting at least one of the decode lines in the direction of a second redundancy selecting line positioned at the other end among the selecting lines or both of the first and second operations when any fault occurs in a plurality of selecting lines. The semiconductor memory device preferably includes two or more first redundancy selecting lines positioned at one of the ends of a plurality of selecting lines, two or more second redundancy selecting lines positioned at the other end, and first and second switch units disposed in two stages. When any fault selecting line occurs, the first switch unit executes a first switch operation for shifting at least one of the decode signal lines in the direction of the first redundancy selecting line or a second switch operation for shifting the same in the direction of the second redundancy selecting line, or the second switch unit executes a third switch operation for shifting at least one decode signal line in the direction of the first redundancy selecting line or a fourth switch operation for shifting it in the direction of the second redundancy selecting line.

摘要翻译： 具有移位冗余功能的半导体存储器件包括用于将解码地址信号的多条解码信号线与多条选择线和冗余选择线可变地连接的开关电路，并且执行用于移位多个选择线和冗余选择线中的至少一个的切换操作 在位于多个选择线中的一端的第一冗余选择线的方向上的解码线的第二切换操作或用于沿着位于所述多个选择线的第二冗余选择线的方向移位至少一条解码线的第二切换操作 在多个选择线中发生任何故障时，选择线中的另一端或第一和第二操作两者。 半导体存储器件优选地包括位于多个选择线的一端的两个或更多个第一冗余选择线，以及位于另一端的两个或更多个第二冗余选择线以及分两个阶段布置的第一和第二开关单元。 当发生任何故障选择线时，第一开关单元执行第一开关操作，用于沿第一冗余选择线的方向移位至少一个解码信号线，或者执行第二开关操作，以使其在第二冗余选择线的方向上移位 冗余选择线或者第二开关单元执行用于在第一冗余选择线的方向上移位至少一个解码信号线的第三开关操作或者用于在第二冗余选择线的方向上移位的第四开关操作。

公开(公告)号：US6052301A

公开(公告)日：2000-04-18

申请号：US272296

申请日：1999-03-19

申请人： Toshimi Ikeda ,  Kuninori Kawabata ,  Masato Takita

发明人： Toshimi Ikeda ,  Kuninori Kawabata ,  Masato Takita

IPC分类号： H01L27/10 ,  G11C7/18 ,  G11C8/14 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C8/14

摘要： According to the present invention, the main word lines arranged in a row direction have a linear pattern shape, and in the region where sub word decoder circuits are formed, the pattern of the main word lines has a shape whereby the pattern branches and splits into a plurality of lines and then reconverges, in the direction of the row. In the region where the line splits, relatively small island-shaped patterns of the conducting layer are located, forming nodes which have a difference electric potential from the main word lines. The main word lines are constituted by a first metal conducting layer, similarly to the prior art. In other words, small island-shaped metal layer patterns, which are electrically different from the main word lines are formed inside the conducting metal layer pattern constituting the main word lines, similarly to island formed in the middle of a river, for example.

摘要翻译： 根据本发明，排列在行方向上的主字线具有线状图案形状，在形成子字译码器电路的区域中，主字线的图形具有图案分支并分成 多行，然后在行的方向上重新转换。 在分割线的区域中，导电层的相对较小的岛状图形被定位，形成与主字线具有差电位的节点。 与现有技术类似，主字线由第一金属导电层构成。 换句话说，与构成主字线的导电金属层图案的内部形成有与主字线电性不同的小岛状金属层图案，与形成在河道中部的岛类似。

公开(公告)号：US5661340A

公开(公告)日：1997-08-26

申请号：US141691

申请日：1993-10-26

申请人： Taiji Ema ,  Masaaki Higashitani ,  Toshimi Ikeda ,  Michiari Kawano ,  Hiroshi Nomura ,  Masaya Katayama ,  Masahiro Kuwamura

发明人： Taiji Ema ,  Masaaki Higashitani ,  Toshimi Ikeda ,  Michiari Kawano ,  Hiroshi Nomura ,  Masaya Katayama ,  Masahiro Kuwamura

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L23/02 ,  H01L21/265

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.

摘要翻译： 一种用于制造动态随机存取存储器的方法，包括以下步骤：在半导体衬底中形成扩散区，在半导体衬底上提供绝缘层，在绝缘层上形成接触孔，露出接触孔处的扩散区，沉积 在绝缘层上形成非晶状态的半导体层，使得半导体层经由接触孔与暴露的扩散区域形成紧密接触，构图半导体层以形成电容器电极，在电容器电极上沉积电介质膜，使得 所述电介质膜覆盖电容器电极; 以及沉积半导体材料以形成相对的电极，使得相对电极将电容器电极埋在下面，同时与覆盖电容器电极的电介质膜形成紧密接触。

公开(公告)号：US5652167A

公开(公告)日：1997-07-29

申请号：US83371

申请日：1993-06-29

申请人： Motoo Nakano ,  Hiroshi Nomura ,  Masaya Katayama ,  Toshimi Ikeda ,  Fumihiko Inoue ,  Junichi Ishikawa ,  Masahiro Kuwamura

发明人： Motoo Nakano ,  Hiroshi Nomura ,  Masaya Katayama ,  Toshimi Ikeda ,  Fumihiko Inoue ,  Junichi Ishikawa ,  Masahiro Kuwamura

IPC分类号： B81B3/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/306 ,  H01L21/70

CPC分类号： B81B3/0005 ,  B81C1/0092 ,  H01L21/02063 ,  H01L28/87 ,  Y10T428/24744 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/8305

摘要： Micro-structures comprising at least a structural member, which is liable to be bent under an external force and formed so as to leave a space between the member and another member liable to be bent and/or other rigid component, are successfully treated using a treating liquid, without suffering permanent deformation resulting from the use of the treating liquid, by removing the micro-structures from the liquid to an environment having a pressure less than the atmospheric pressure; or displacing the micro-structures from the treating liquid to another treating liquid having a smaller surface tension than that of the former liquid, and then removing the micro-structures from the latter liquid; or drying the micro-structures removed from the treating liquid by exposing the same to vapor of a liquid having a smaller surface tension than that of the treating liquid; or removing the micro-structures from the treating liquid to the atmosphere, and drying them using an energy beam of high intensity or an ultrasonic wave. Micro-structures are also disclosed which comprise at least a member liable to be bent but are capable of avoiding permanent deformation of the member resulting from a treatment using a liquid.

摘要翻译： 至少包括结构构件的微结构，其在外力下容易弯曲并且形成为在构件和易于弯曲的另一构件和/或其他刚性构件之间留下空间，成功地使用 处理液体，而不会由于使用处理液而导致永久变形，通过将微结构从液体移除到具有小于大气压力的压力的环境中; 或将微结构从处理液体移位到具有比前者液体小的表面张力的另一处理液，然后从后一液体中除去微结构; 或者通过将从处理液中除去的微结构暴露于具有比处理液的表面张力小的液体的蒸汽，来干燥微结构; 或将微结构从处理液中除去至大气，并使用高强度能量束或超声波干燥它们。 还公开了微结构，其包括至少一个易于弯曲的构件，但是能够避免由使用液体的处理引起的构件的永久变形。

公开(公告)号：US07184296B2

公开(公告)日：2007-02-27

申请号：US11069940

申请日：2005-03-03

申请人： Atsushi Hatakeyama ,  Toshimi Ikeda ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

发明人： Atsushi Hatakeyama ,  Toshimi Ikeda ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

IPC分类号： G11C11/00

CPC分类号： G11C16/28

摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.

摘要翻译： 存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103） ）。 预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。 负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。 放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。