公开(公告)号：US4146413A

公开(公告)日：1979-03-27

申请号：US738059

申请日：1976-11-02

申请人： Toshio Yonezawa ,  Toshio Mitsuno ,  Kiyoshi Takaoki ,  Takashi Ajima

发明人： Toshio Yonezawa ,  Toshio Mitsuno ,  Kiyoshi Takaoki ,  Takashi Ajima

IPC分类号： H01L29/78 ,  H01L21/205 ,  H01L21/225 ,  H01L21/28 ,  H01L21/321 ,  H01L29/04 ,  H01L29/43 ,  H01L29/861 ,  H01L21/20

CPC分类号： H01L21/321 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/04 ,  Y10S148/124

摘要： A method of producing a semiconductor device, comprising the steps of forming a polycrystalline semiconductor layer on the exposed surface of a single crystalline semiconductor substrate, the substrate containing an impurity of one conductivity type and the polycrystalline layer an impurity of the other conductivity type, and heating the polycrystalline layer for the activation thereof at a temperature substantially preventing the impurity contained therein from being diffused into the substrate. The crystal of the substrate is kept free from lattice defect since the impurity is not diffused thereinto. In addition, this method prevents a short circuit from occurring between semiconductor regions of differing conductivity types which would otherwise be caused by deviation in the location of a mask used in the photoetching step.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在单晶半导体衬底的暴露表面上形成多晶半导体层，所述衬底含有一种导电类型的杂质，并且所述多晶层为另一种导电类型的杂质;以及 在基本上防止其中包含的杂质扩散到基底中的温度下加热多晶层以使其活化。 由于杂质不会扩散，所以基板的晶体保持没有晶格缺陷。 此外，这种方法防止了在不同导电类型的半导体区域之间发生短路，否则将由光刻步骤中使用的掩模位置的偏差引起。

公开(公告)号：US4123564A

公开(公告)日：1978-10-31

申请号：US746897

申请日：1976-12-02

申请人： Takashi Ajima ,  Kiyoshi Takaoki ,  Toshio Yonezawa

发明人： Takashi Ajima ,  Kiyoshi Takaoki ,  Toshio Yonezawa

IPC分类号： H01L29/73 ,  H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/8222 ,  B05D5/12 ,  H01L21/22

CPC分类号： H01L21/8222 ,  H01L21/314 ,  H01L21/321 ,  H01L21/32132 ,  Y10S438/911 ,  Y10S438/958

摘要： A method of producing a semiconductor device comprises removing all of the masking films used for forming desired semiconductor regions in the substrate, newly forming a first insulation film and selectively forming a second insulation film on predetermined portions of the first insulation film by the use of a polycrystalline silicon film as the mask.

摘要翻译： 一种半导体器件的制造方法，其特征在于，除去在所述基板中形成期望的半导体区域的所有掩模膜，新形成第一绝缘膜，并且在所述第一绝缘膜的预定部分上选择性地形成第二绝缘膜， 多晶硅膜作为掩模。

公开(公告)号：US4792534A

公开(公告)日：1988-12-20

申请号：US942076

申请日：1986-12-15

申请人： Hitoshi Tsuji ,  Tiharu Kato ,  Kiyoshi Takaoki

发明人： Hitoshi Tsuji ,  Tiharu Kato ,  Kiyoshi Takaoki

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/308

CPC分类号： H01L21/0337

摘要： A method of manufacturing a semiconductor device having a submicron pattern. A p-type semiconductor layer is formed on an n-type semiconductor substrate. Insulating films are formed on the p-type semiconductor layer. A first mask layer, such as an aluminum layer having an etching rate different from that of the insulating films, is formed on the insulating films. A second mask layer having an etching rate different from that of the first mask layer, is formed on the first mask layer. The second mask layer is patterned. A coating film having an etching rate different from that of the first insulating film, is formed on the resultant structure. The coating film is etched to be left on a side wall of the patterned second mask layer. The first mask layer is patterned, using the residual coating film and the patterned second mask layer as masks, and a pattern finer than that of the resist is formed in the first mask layer. The insulating film is patterned, using the patterned first mask layer, and a pattern finer than that of the resist is formed in the insulating film. In the p-type semiconductor layer n+-type emitter and p+ base leading regions are formed, and the n-type semiconductor layer serves as a collector.

摘要翻译： 一种制造具有亚微米图案的半导体器件的方法。 p型半导体层形成在n型半导体衬底上。 绝缘膜形成在p型半导体层上。 在绝缘膜上形成第一掩模层，例如具有与绝缘膜不同的蚀刻速率的铝层。 在第一掩模层上形成具有不同于第一掩模层的蚀刻速率的第二掩模层。 第二掩模层被图案化。 在所得结构上形成具有不同于第一绝缘膜的蚀刻速率的涂膜。 蚀刻该涂膜以留在图案化的第二掩模层的侧壁上。 使用残留涂膜和图案化的第二掩模层作为掩模对第一掩模层进行构图，并且在第一掩模层中形成比抗蚀剂更细的图案。 使用图案化的第一掩模层对绝缘膜进行图案化，并且在绝缘膜中形成比抗蚀剂更细的图案。 在p型半导体层中，形成n +型发射极和p +基极引线区，并且n型半导体层用作集电极。