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1.发明授权
公开(公告)号：US3958658A
公开(公告)日：1976-05-25
申请号：US505460
申请日：1974-09-12
CPC分类号： B60R22/48 , B60R2022/4816 , B60R2022/4891
摘要： The shift mechanism of an automotive power transmission system is locked in the neutral or parking position by a locking device which is responsive to completion or incompletion of a prescribed manipulative procedure to render a safety device such as a safety belt arrangement into a proper protective position, the locking device including a cam movable with any suitable member of the shift mechanism and a catch member which is moved into locking engagement with the cam if the prescribed manipulative steps to move the safety device into the proper protective position is incomplete.
摘要翻译： 汽车动力传动系统的换档机构通过锁定装置锁定在中立或停车位置，所述锁定装置响应于完成或不完成规定的操纵过程以使诸如安全带装置的安全装置成为适当的保护位置， 所述锁定装置包括可移动所述换档机构的任何合适构件的凸轮和如果将所述安全装置移动到适当的保护位置中的所述规定的操纵步骤，则所述卡扣构件被移动成与所述凸轮锁定接合。
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公开(公告)号：US08166363B2
公开(公告)日：2012-04-24
申请号：US12066641
申请日：2006-09-07
IPC分类号： H03M13/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数的计算的校验节点计算（x）及其非线性函数的反函数＆phgr（-1），以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收表示具有固定量化宽度的数值的定点量化值，并将非线性函数＆amp;（x）的计算结果作为半浮点数量化 值，其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数的计算结果＆phgr; -1（ x）作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。
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公开(公告)号：US08103945B2
公开(公告)日：2012-01-24
申请号：US11959551
申请日：2007-12-19
IPC分类号： G06F11/00
CPC分类号： H03M13/114 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936 , H03M13/2948 , H03M13/3905 , H03M13/4146
摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.
摘要翻译： 一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播 值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播 可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。
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公开(公告)号：US08098775B2
公开(公告)日：2012-01-17
申请号：US12403445
申请日：2009-03-13
IPC分类号： H04L27/06
CPC分类号： H03M13/41
摘要： A data processing apparatus includes: a branch-metric computation section configured to compute a branch metric; a state-metric computation section configured to compute a state metric; a detection section configured to detect a minimum state metric; a storage section configured to store states as surviving states; and a selection section configured to select a candidate.
摘要翻译： 数据处理装置包括：分支度量计算部，被配置为计算分支度量; 配置为计算状态度量的状态度量计算部分; 检测部，被配置为检测最小状态度量; 存储部，被配置为将状态存储为存活状态; 以及选择部，被配置为选择候选。
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公开(公告)号：US20090304111A1
公开(公告)日：2009-12-10
申请号：US12066641
申请日：2006-09-07
IPC分类号： H03K9/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数phi（x）及其反函数phi-1（x）的计算的校验节点计算，以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收具有固定量化宽度的表示数值的定点量化值，并将非线性函数phi（x）的计算结果输出为半浮点量化值 其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数phi-1（x）的计算结果， 作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。
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公开(公告)号：US07051270B2
公开(公告)日：2006-05-23
申请号：US10110670
申请日：2001-08-20
CPC分类号： H03M13/3905 , H03M13/258 , H03M13/27 , H03M13/29 , H03M13/2957 , H03M13/2972 , H03M13/6337 , H03M13/6577 , H03M13/658
摘要： A decoder that receives, as input, probability information AMP/CR×yt. This probability information is obtained by dividing a channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output CI×Iλt and/or external information 1/CA×EXt using additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.
摘要翻译： 接收作为输入的概率信息的解码器。 该概率信息是通过将通过接收值y
T 与预定系数AMP乘以获得的信道值除以第一加法系数C SUB来获得的，以用于调节 通过将先验概率信息APP＆lt; T＆gt;＆lt;＆gt;＆lt; T＆gt;获得的概率信息1 / C A xAPP＆lt; SUB>通过第二加法系数C A A A的倒数，用于将先验概率信息APP 的振幅调整到软输出解码电路。 可以是大规模集成电路的软输出解码电路生成日志软输出C 1和/或外部信息1 / C＆lt; 使用用于调节软输出解码电路内部的算术运算幅度的加法系数的XEXT。 -
7.发明申请Decoding method, decoding device, program, recording/reproduction device and method, and reproduction device and method 失效解码方法，解码装置，程序，记录/再现装置和方法以及再现装置和方法公开(公告)号：US20060015791A1
公开(公告)日：2006-01-19
申请号：US10523452
申请日：2004-05-28
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G11B20/18 , G11B20/1866 , G11B2020/1836 , H03M13/1111 , H03M13/1191 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936
摘要： The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing, performs linear combination for rows of a parity check matrix included in an obtained reception word, and generates a parity check matrix according to the linear-combination result, thereby reducing the density of the parity check matrix used for decoding, at step S21. Then, at step S22, an LDPC decoding unit performs decoding by using a sum product algorithm (SPA) by using the parity check matrix whose density is reduced through the processing performed at step S21. Where the processing at step S22 is finished, the LDPC decoding unit finishes decoding for the reception word. The present invention can be used for an error-correction system.
摘要翻译： 本发明涉及适用于对通过使用环R上的线性码编码的编码数据进行解码的解码方法和解码器，程序，记录和再现装置和方法以及再现装置和方法。 低密度处理单元执行奇偶校验矩阵低密度处理，对获得的接收字中包含的奇偶校验矩阵的行进行线性组合，并根据线性组合结果生成奇偶校验矩阵，从而减少 在步骤S21中用于解码的奇偶校验矩阵的密度。然后，在步骤S22，LDPC解码单元通过使用通过使用密度减小的奇偶校验矩阵的和乘积算法（SPA）来执行解码 在步骤S2执行的处理。在步骤S22的处理完成的情况下，LDPC解码单元完成接收字的解码。 本发明可以用于纠错系统。
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8.发明授权Method and apparatus for reproducing data and method and apparatus for recording and/or reproducing data 失效用于再现数据的方法和装置，用于记录和/或再现数据的方法和装置公开(公告)号：US06798593B2
公开(公告)日：2004-09-28
申请号：US09814548
申请日：2001-03-22
IPC分类号： G11B509
CPC分类号： H03M13/2957 , G11B20/10194 , G11B20/1426 , G11B20/1833 , G11B20/1866 , G11B2020/1434 , G11B2020/1446 , H03M13/6325
摘要： A magnetic recording and/or reproducing apparatus which achieves high performance encoding and high efficiency decoding to lower the decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes, in its recording system, an error correction coder 51 for error correction coding input data and an interleaver 52 for scrambling the sequence of data supplied from the error correction coder 51. The magnetic recording and/or reproducing apparatus 50 also includes, in its reproducing system, s modulation and error correction turbo decoder 64 provided with a deinterleaver for scrambling and re-arraying the sequence of the input data such as to restore the sequence of input data re-arrayed by the interleaver 52 to an original bit sequence, an error correction soft decoder for decoding data supplied from the deinterleaver and with a second interleaver for scrambling and re-arraying the sequence of data given as a difference between data output from the error correction soft decoder and data output from the deinterleaver.
摘要翻译： 一种实现高性能编码和高效率解码以降低解码错误率的磁记录和/或再现装置。 磁记录和/或再现装置50在其记录系统中包括用于纠错编码输入数据的纠错编码器51和用于对从纠错编码器51提供的数据序列进行加扰的交织器52.磁记录和/ 或再现装置50在其再现系统中还包括设置有去交织器的调制和纠错turbo解码器64，用于对输入数据的序列进行加扰和重新排列，以便恢复由所述解交织器重新排列的输入数据的序列 交织器52到原始比特序列，纠错软解码器，用于对从解交织器提供的数据进行解码，以及用于第二交织器，用于加扰和重新排列作为从纠错软解码器输出的数据与数据之间的差异的数据序列 从解交织器输出。
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公开(公告)号：US06668351B1
公开(公告)日：2003-12-23
申请号：US09601976
申请日：2000-08-10
申请人： Tamotsu Ikeda , Toshiyuki Miyauchi
发明人： Tamotsu Ikeda , Toshiyuki Miyauchi
IPC分类号： H03M1303
CPC分类号： H04L1/0059 , H03M13/4107 , H03M13/6325 , H03M13/6502 , H04L1/0041 , H04L1/0045
摘要： The deterioration of an error characteristic obtained at a point where a transfer method is changed is suppressed. A first adder calculates a SM value obtained when the state 00 is changed to the state 00, and outputs it to a comparator. A second adder calculates a SM value obtained when the state 01 is changed to the state 00, and outputs it to the comparator. The comparator compares the SM values, selects a path having the larger likelihood, and outputs to a register having a set and a reset. An ACS controller detects a condition in which the state transition of fixed information TAB1 is uniquely determined, and outputs a reset signal to the register having a set and a reset, which stores the SM value of that state, to set the value of the register to zero. The ACS controller 85 also outputs set signals to registers having sets and resets, which store the SM values of the states other than the state 00 of the fixed information TAB1, to set them to the maximum value.
摘要翻译： 在转印方法改变的点处获得的误差特性的劣化被抑制。 第一加法器计算当状态00改变为状态00时获得的SM值，并将其输出到比较器。 第二加法器计算当状态01改变为状态00时获得的SM值，并将其输出到比较器。 比较器比较SM值，选择具有较大似然度的路径，并输出到具有置位和复位的寄存器。 ACS控制器检测固定信息TAB1的状态转移被唯一地确定的状态，并且向具有存储该状态的SM值的集合和复位的寄存器输出复位信号，以设置寄存器的值 到零。 ACS控制器85还将设置信号输出到具有集合和复位的寄存器，该寄存器存储除固定信息TAB1的状态00之外的状态的SM值，以将它们设置为最大值。
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10.发明授权公开(公告)号：US06360346B1
公开(公告)日：2002-03-19
申请号：US09140005
申请日：1998-08-26
IPC分类号： G11C2900
CPC分类号： G11C29/42
摘要： A storage unit is provided which is capable of preventing the occurrence of readout errors even if two or more errors arise within a code, and a storage unit checking method is offered which can improve the productivity. Write data produced by BCH-encoding and compacting data s1 inputted into a flash memory, capable of correcting two errors within a code in an encoder, is written in a cell array. Data read out from the cell array 3 is error-corrected and decoded in an error correction/encoder to generate output data. In the check to be made at manufacturing (or putting on the market), examination data written in advance is successively read out by one block so that the errors within each code is counted. If the number of errors assumes 1 or less, that code is subjected to error correction, whereas the block including a code whose error number is 2 or more is treated as a defective block. The acceptance or failure is determined depending upon, for example, whether the rate of the number of defective blocks to the total number of blocks is below or not less than 1%.
摘要翻译： 提供了一种存储单元，其能够防止在代码中出现两个或更多个错误的情况下发生读出错误，并且提供可以提高生产率的存储单元检查方法。 写入通过BCH编码产生的数据和输入到闪存中的压缩数据s1，其能够校正编码器中的代码内的两个错误，被写入单元阵列中。 从单元阵列3读出的数据在误差校正/编码器中进行纠错和解码以产生输出数据。 在制造（或投放市场）的检查中，预先写入的检查数据被一个块连续地读出，从而对每个代码中的错误进行计数。 如果错误数假定为1或更小，则该代码进行错误校正，而包含错误号为2或更大的代码的块被视为缺陷块。 接收或故障根据例如有缺陷块的数量与总块数的比率是低于还是不小于1％来确定。
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