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    Trench-type semiconductor memory device
    3.
    发明授权
    Trench-type semiconductor memory device 失效
    沟槽型半导体存储器件

    公开(公告)号：US5861649A

    公开(公告)日：1999-01-19

    申请号：US871530

    申请日：1992-04-21

    申请人： Hiroyuki Yoshida ,  Takayuki Niuya ,  Toshiyuki Nagata ,  Yoichi Miyai ,  Yoshihiro Ogata

    发明人： Hiroyuki Yoshida ,  Takayuki Niuya ,  Toshiyuki Nagata ,  Yoichi Miyai ,  Yoshihiro Ogata

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/92 ,  H01L29/76

    CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L28/40

    摘要： A dynamic RAM in which a groove (20) is formed on the main surface of a semiconductor substrate; a highly concentrated semiconductor layer (80) having one conductive type is formed inside the groove (20) to a depth sufficient to contain the first and second impurity diffusion areas (53) and (22), which are formed on the top of this groove and have the opposite conductive type; a capacitor C.sub.1 formed inside the groove (20), while a transfer gate Tr.sub.1 is formed on the highly concentrated semiconductor layer (80); and the diffusion area (53) is used to connect them.

    摘要翻译： 一种动态RAM，其中在半导体衬底的主表面上形成有沟槽（20）; 在凹槽（20）的内部形成有一个具有一种导电类型的高度集中的半导体层（80），其深度足以容纳形成在该槽的顶部上的第一和第二杂质扩散区域（53）和（22） 并具有相反的导电类型; 形成在所述槽（20）内部的电容器C1，同时在所述高度集中的半导体层（80）上形成传输门Tr1。 并且扩散区域（53）用于连接它们。

    Method of forming a trench-type semiconductor memory device
    4.
    发明授权
    Method of forming a trench-type semiconductor memory device 失效
    形成沟槽型半导体存储器件的方法

    公开(公告)号：US5804478A

    公开(公告)日：1998-09-08

    申请号：US698433

    申请日：1996-08-15

    申请人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya ,  Yoshihiro Ogata

    发明人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya ,  Yoshihiro Ogata

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10861 ,  H01L28/40

    摘要： A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film(54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell. Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.

    摘要翻译： 一种具有这样的结构的半导体器件，其特征在于，预先连接到绝缘膜（54）的步骤（54a）形成导电膜（90），并且导电层（63）与上述导电膜 被涂覆以形成存储单元的侧面接触。 即使在导电层（63）中发生断裂的情况下，仍然通过导电膜（90）保持导电，实际上不发生断线。 此外，可以通过例如在不施加特殊掩模的情况下回蚀刻方法来形成上述导电层的图案; 因此，简化了制造过程。

    French-type semiconductor memory device with enhanced trench capacitor-transistor connection
    5.
    发明授权
    French-type semiconductor memory device with enhanced trench capacitor-transistor connection 失效
    法国式半导体存储器件，具有增强的沟槽电容 - 晶体管连接

    公开(公告)号：US5563433A

    公开(公告)日：1996-10-08

    申请号：US883502

    申请日：1992-05-15

    申请人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya ,  Yoshihiro Ogata

    发明人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya ,  Yoshihiro Ogata

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L28/40

    摘要： A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film (54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell.Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via substrate electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.

    摘要翻译： 一种具有这样的结构的半导体器件，其特征在于，预先连接到绝缘膜（54）的步骤（54a）形成导电膜（90），并且导电层（63）与上述导电膜 被涂覆以形成存储单元的侧面接触。 即使在导电层（63）中发生断裂的情况下，仍然通过基板导电膜（90）保持导电性，实际上不发生断线。 此外，可以通过例如在不施加特殊掩模的情况下回蚀刻方法来形成上述导电层的图案; 因此，简化了制造过程。

    Method for fabricating an open can-type stacked capacitor on an uneven surface
    6.
    发明授权
    Method for fabricating an open can-type stacked capacitor on an uneven surface 有权
    在不平坦表面上制造开罐式叠层电容器的方法

    公开(公告)号：US06291293B1

    公开(公告)日：2001-09-18

    申请号：US09373484

    申请日：1999-08-12

    申请人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku ,  Toshiyuki Nagata

    发明人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku ,  Toshiyuki Nagata

    IPC分类号： H01L218242

    CPC分类号： H01L27/10855 ,  H01L28/92

    摘要： An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150) is formed in an outer surface (32, 132) of the conductive layer (30, 130). A base (72, 172, 202) of a first electrode (70, 170, 200) is formed by removing a predetermined thickness (66, 166) of at least part of the conductive layer (30, 130). The base (72, 172, 202) is made of a portion of the conductive layer (30, 130) underlying the step (50, 150) by the predetermined thickness (66, 166). A sidewall (74, 174) of the first electrode (70, 170, 200) is formed. A dielectric layer (80) is formed outwardly of the first electrode (70, 170, 200). A second electrode (82) of the capacitor is formed outwardly of the dielectric layer (80).

    摘要翻译： 通过在基本上不平坦的表面（12,112）外部形成导电层（30,130）来制造开放式罐式叠层电容器。 在导电层（30,130）的外表面（32,132）中形成台阶（50,150）。 通过去除导电层（30,130）的至少一部分的预定厚度（66,166）来形成第一电极（70,170,200）的基底（72,172,202）。 基座（72,172,202）由位于台阶（50,150）下方的预定厚度（66,166）的导电层（30,130）的一部分制成。 第一电极（70,170,200）的侧壁（74,174）形成。 介电层（80）形成在第一电极（70,170,200）的外侧。 电容器的第二电极（82）形成在电介质层（80）的外侧。

    Method for fabricating an open can-type stacked capacitor on an uneven surface
    7.
    发明授权
    Method for fabricating an open can-type stacked capacitor on an uneven surface 有权
    在不平坦表面上制造开罐式叠层电容器的方法

    公开(公告)号：US06580112B2

    公开(公告)日：2003-06-17

    申请号：US09855401

    申请日：2001-05-15

    申请人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku ,  Toshiyuki Nagata

    发明人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku ,  Toshiyuki Nagata

    IPC分类号： H01L27108

    CPC分类号： H01L27/10855 ,  H01L28/92

    摘要： An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150) is formed in an outer surface (32, 132) of the conductive layer (30, 130). A base (72, 172, 202) of a first electrode (70, 170, 200) is formed by removing a predetermined thickness (66, 166) of at least part of the conductive layer (30, 130). The base (72, 172, 202) is made of a portion of the conductive layer (30, 130) underlying the step (50, 150) by the predetermined thickness (66, 166). A sidewall (74, 174) of the first electrode (70, 170, 200) is formed. A dielectric layer (80) is formed outwardly of the first electrode (70, 170, 200). A second electrode (82) of the capacitor is formed outwardly of the dielectric layer (80).

    摘要翻译： 通过在基本上不平坦的表面（12,112）外部形成导电层（30,130）来制造开放式罐式叠层电容器。 在导电层（30,130）的外表面（32,132）中形成台阶（50,150）。 通过去除导电层（30,130）的至少一部分的预定厚度（66,166）来形成第一电极（70,170,200）的基底（72,172,202）。 基座（72,172,202）由位于台阶（50,150）下方的预定厚度（66,166）的导电层（30,130）的一部分制成。 形成第一电极（70,170,200）的侧壁（74,174）。 电介质层（80）形成在第一电极（70,170,200）的外侧。 电容器的第二电极（82）形成在电介质层（80）的外侧。

    Method of fabricating random access memory device having sidewall insulating layer on the laminate structure
    8.
    发明授权
    Method of fabricating random access memory device having sidewall insulating layer on the laminate structure 失效
    制造在层叠结构上具有侧壁绝缘层的随机存取存储器件的方法

    公开(公告)号：US5470777A

    公开(公告)日：1995-11-28

    申请号：US248830

    申请日：1994-05-25

    申请人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya

    发明人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/00 ,  H01L21/70

    CPC分类号： H01L21/768 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10873

    摘要： A semiconductor device in which a bit line (41), which is adhered to a contact hole (49) between polysilicon gate electrodes (35) and (36), is directly connected with an SiO.sub.2 film (53) having the same pattern on the gate electrodes; wherein an Si.sub.3 N.sub.4 layer (56) is buried outside the contact areas between the gate electrodes to approximately the same height as the SiO.sub.2 layer (53). The interlayer insulating film of the conventional memory cells array unit is no longer required, and it is not necessary to form contact holes in the interlayer insulating film. As a result, even if the gaps between the gates are designed to be small, there will be no short-circuiting between the bit line and word lines due to mask shifting, etc., making it possible to offer a highly integrated, highly reliable device.

    摘要翻译： 一种半导体器件，其中粘附到多晶硅栅电极（35）和（36）之间的接触孔（49）上的位线（41）与具有相同图案的SiO 2膜（53）直接连接 栅电极; 其中Si 3 N 4层（56）被掩埋在栅电极之间的接触区域的外部，与SiO 2层（53）大致相同的高度。 不再需要传统的存储单元阵列单元的层间绝缘膜，并且不需要在层间绝缘膜中形成接触孔。 结果，即使栅极之间的间隙被设计为小，由于掩模移位等，位线和字线之间也不会发生短路，使得可以提供高集成度，高可靠性 设备。