公开(公告)号：US5317177A

公开(公告)日：1994-05-31

申请号：US889323

申请日：1992-05-27

申请人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya ,  Yoshihiro Ogata ,  Katsushi Boku ,  Yoichi Miyai

发明人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya ,  Yoshihiro Ogata ,  Katsushi Boku ,  Yoichi Miyai

IPC分类号： H01L21/205 ,  H01L21/265 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/68 ,  H01L29/78 ,  H01L29/92

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100). It is possible to form the element areas according to designs, and it is also possible to flatten the surface without wire cutting in the conductive layer.

摘要翻译： 一种半导体器件，其中沟槽形沟槽（20）和凹陷（100）形成为在半导体衬底的一侧上是连续的 其中上述凹槽和上述凹陷掩埋有多晶硅导电层（103），其导电层的顶部被转换成绝缘体（102），其绝缘膜（102）的底部包含在凹部（100）中， 。 可以根据设计形成元件区域，并且还可以在导电层中没有线切割的同时使表面变平。

公开(公告)号：US5470778A

公开(公告)日：1995-11-28

申请号：US251866

申请日：1994-05-31

申请人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya ,  Yoshihiro Ogata ,  Katsushi Boku ,  Yoichi Miyai

发明人： Toshiyuki Nagata ,  Hiroyuki Yoshida ,  Takayuki Niuya ,  Yoshihiro Ogata ,  Katsushi Boku ,  Yoichi Miyai

IPC分类号： H01L21/205 ,  H01L21/265 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100).

摘要翻译： 一种半导体器件，其中沟槽形沟槽（20）和凹陷（100）形成为在半导体衬底的一侧上是连续的 其中上述凹槽和上述凹陷掩埋有多晶硅导电层（103），其导电层的顶部被转换成绝缘体（102），其绝缘膜（102）的底部包含在凹陷（100）中， 。

公开(公告)号：US06291293B1

公开(公告)日：2001-09-18

申请号：US09373484

申请日：1999-08-12

申请人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku ,  Toshiyuki Nagata

发明人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku ,  Toshiyuki Nagata

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L28/92

摘要： An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150) is formed in an outer surface (32, 132) of the conductive layer (30, 130). A base (72, 172, 202) of a first electrode (70, 170, 200) is formed by removing a predetermined thickness (66, 166) of at least part of the conductive layer (30, 130). The base (72, 172, 202) is made of a portion of the conductive layer (30, 130) underlying the step (50, 150) by the predetermined thickness (66, 166). A sidewall (74, 174) of the first electrode (70, 170, 200) is formed. A dielectric layer (80) is formed outwardly of the first electrode (70, 170, 200). A second electrode (82) of the capacitor is formed outwardly of the dielectric layer (80).

摘要翻译： 通过在基本上不平坦的表面（12,112）外部形成导电层（30,130）来制造开放式罐式叠层电容器。 在导电层（30,130）的外表面（32,132）中形成台阶（50,150）。 通过去除导电层（30,130）的至少一部分的预定厚度（66,166）来形成第一电极（70,170,200）的基底（72,172,202）。 基座（72,172,202）由位于台阶（50,150）下方的预定厚度（66,166）的导电层（30,130）的一部分制成。 第一电极（70,170,200）的侧壁（74,174）形成。 介电层（80）形成在第一电极（70,170,200）的外侧。 电容器的第二电极（82）形成在电介质层（80）的外侧。

公开(公告)号：US06580112B2

公开(公告)日：2003-06-17

申请号：US09855401

申请日：2001-05-15

申请人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku ,  Toshiyuki Nagata

发明人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku ,  Toshiyuki Nagata

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L28/92

摘要： An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150) is formed in an outer surface (32, 132) of the conductive layer (30, 130). A base (72, 172, 202) of a first electrode (70, 170, 200) is formed by removing a predetermined thickness (66, 166) of at least part of the conductive layer (30, 130). The base (72, 172, 202) is made of a portion of the conductive layer (30, 130) underlying the step (50, 150) by the predetermined thickness (66, 166). A sidewall (74, 174) of the first electrode (70, 170, 200) is formed. A dielectric layer (80) is formed outwardly of the first electrode (70, 170, 200). A second electrode (82) of the capacitor is formed outwardly of the dielectric layer (80).

摘要翻译： 通过在基本上不平坦的表面（12,112）外部形成导电层（30,130）来制造开放式罐式叠层电容器。 在导电层（30,130）的外表面（32,132）中形成台阶（50,150）。 通过去除导电层（30,130）的至少一部分的预定厚度（66,166）来形成第一电极（70,170,200）的基底（72,172,202）。 基座（72,172,202）由位于台阶（50,150）下方的预定厚度（66,166）的导电层（30,130）的一部分制成。 形成第一电极（70,170,200）的侧壁（74,174）。 电介质层（80）形成在第一电极（70,170,200）的外侧。 电容器的第二电极（82）形成在电介质层（80）的外侧。

公开(公告)号：US06204118B1

公开(公告)日：2001-03-20

申请号：US09373214

申请日：1999-08-12

申请人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku

发明人： Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku

IPC分类号： H01L218242

CPC分类号： H01L28/92 ,  H01L27/10852

摘要： An open can-type stacked capacitor is fabricated on local topology by forming a conductive layer (30) outwardly of an insulator (14, 86) and an access line (16, 18) extending from the insulator (14, 86). A mask (40) is formed outwardly of the conductive layer (30). A first electrode (50, 80) is formed by removing at least part of the conductive layer (30) exposed by the mask (40). The first electrode (50, 80) includes an annular sidewall (52) having a first segment (54, 82) disposed on the insulator (14, 86) and a second, opposite segment (56) disposed on the access line (16, 18). A dielectric layer (60) is formed outwardly of the first electrode (50, 80). A second electrode (62) is formed outwardly of the dielectric layer (60).

摘要翻译： 通过在绝缘体（14,86）之外形成导电层（30）和从绝缘体（14,86）延伸的接入线（16,18），在局部拓扑上制造开放式罐式叠层电容器。 在导电层（30）的外侧形成掩模（40）。 通过去除由掩模（40）暴露的导电层（30）的至少一部分来形成第一电极（50,80）。 第一电极（50,80）包括环形侧壁（52），其具有设置在绝缘体（14,86）上的第一段（54,82）和设置在接入线（16）上的第二相对的段（56） 18）。 电介质层（60）形成在第一电极（50,80）的外侧。 第二电极（62）形成在电介质层（60）的外侧。

公开(公告)号：US5734184A

公开(公告)日：1998-03-31

申请号：US770883

申请日：1996-12-20

申请人： Katsuyoshi Andoh ,  Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku

发明人： Katsuyoshi Andoh ,  Yoichi Miyai ,  Masayuki Moroi ,  Katsushi Boku

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10829

摘要： A DRAM uses arcuate moats 18 and wavy bit lines 28, 30 for the array of memory cells. A bit line contact 20 occurs at the apex of the moat and storage node contacts 22, 24 occur at the ends of legs 40, 42 extending from the apex. The wavy bit lines have alternating crests 32, 36 and troughs 34, 38. The bit lines are arranged over the moats with the troughs of each bit line overlying and contacting the apexes of each moat and the crests avoiding any moat. The crests and troughs of the bit lines are offset from one another. In a half-pitch pattern, the troughs of one bit line lie adjacent to the crests of the next bit line. The moats are concave between the legs and the angle between the legs is between about 140 and 170 degrees. The angle between the crests and troughs of the bit lines is between about 110 and 160 degrees. In one embodiment, the central portion 70 between the areas surrounding the storage node contacts is about 10% wider than the areas surrounding the storage node contacts.

摘要翻译： DRAM对于存储器单元阵列使用弧形护城河18和波纹位线28,30。 位线接触20发生在护城河的顶点处，并且存储节点接触件22,24发生在从顶点延伸的腿部40,42的端部处。 波纹位线具有交替的峰32,36和槽34,38。位线布置在护城河上，每个位线的槽谷覆盖并接触每个护城河的顶点并且避免任何护城河。 位线的波峰和波谷彼此偏移。 在半间距图案中，一个位线的槽与下一位线的波峰相邻。 护城河两腿之间是凹的，腿之间的角度在大约140和170度之间。 位线的波峰和波谷之间的角度在约110和160度之间。 在一个实施例中，围绕存储节点触点的区域之间的中心部分70比围绕存储节点触点的区域宽约10％。

公开(公告)号：US06967365B2

公开(公告)日：2005-11-22

申请号：US10620196

申请日：2003-07-15

申请人： Scott Robert Summerfelt ,  Katsushi Boku

发明人： Scott Robert Summerfelt ,  Katsushi Boku

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L28/55 ,  H01L21/76895 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

摘要： Ferroelectric memory cells and fabrication methods are provided in which the memory cell comprises a ferroelectric capacitor in a capacitor layer above a semiconductor body, and a cell transistor with first and second source/drains formed in an active region of the semiconductor body. The active region extends along a first axis in the semiconductor body, and the cell includes a gate electrically coupled with a wordline structure that extends along a second axis, wherein the first axis and the second axis are oblique.

摘要翻译： 提供了铁电存储器单元及制造方法，其中存储单元包括在半导体本体上方的电容器层中的铁电电容器，以及在半导体本体的有源区中形成有第一和第二源极/漏极的单元晶体管。 有源区域沿着半导体本体中的第一轴线延伸，并且电池单元包括与沿着第二轴线延伸的字线结构电耦合的栅极，其中第一轴线和第二轴线是倾斜的。

公开(公告)号：US20050012125A1

公开(公告)日：2005-01-20

申请号：US10620196

申请日：2003-07-15

申请人： Scott Summerfelt ,  Katsushi Boku

发明人： Scott Summerfelt ,  Katsushi Boku

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L28/55 ,  H01L21/76895 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

摘要： Ferroelectric memory cells and fabrication methods are provided in which the memory cell comprises a ferroelectric capacitor in a capacitor layer above a semiconductor body, and a cell transistor with first and second source/drains formed in an active region of the semiconductor body. The active region extends along a first axis in the semiconductor body, and the cell includes a gate electrically coupled with a wordline structure that extends along a second axis, wherein the first axis and the second axis are oblique.

公开(公告)号：US5521116A

公开(公告)日：1996-05-28

申请号：US427479

申请日：1995-04-24

申请人： Katsushi Boku

发明人： Katsushi Boku

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  Y10S148/055 ,  Y10S438/94

摘要： A method for fabricating and for blowing top lead fuses (41 and 42) includes the steps of: (a) forming a conductive top lead fuse (41) on a layer of insulator (45); (b) depositing a layer of top insulator (47) over the top lead fuse at a top to sidewall thickness ratio of approximately 2:1; (c) anisotropically etching the top insulator back universally to a top to sidewall thickness ratio of approximately 1:2. The resulting top lead fuses (30 and 31) are selectively blown explosively out (24) of the top surface of the top insulator.

摘要翻译： 一种用于制造和吹制顶部引线熔丝（41和42）的方法包括以下步骤：（a）在绝缘体层（45）上形成导电顶部引线熔丝（41）; （b）在顶部引线熔丝上以大约2:1的顶部与侧壁厚度比沉积一层顶部绝缘体（47）; （c）将顶部绝缘体各向异性地蚀刻到通常的约1：2的顶部与侧壁厚度之间。 所产生的顶部引线熔断器（30和31）被选择性地从顶部绝缘体顶表面（24）中吹出。