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公开(公告)号:US08445363B2
公开(公告)日:2013-05-21
申请号:US13091153
申请日:2011-04-21
申请人: Tsuo-Wen Lu , I-Ming Lai , Tsung-Yu Hou , Chien-Liang Lin , Wen-Yi Teng , Shao-Wei Wang , Yu-Ren Wang , Chin-Cheng Chien
发明人: Tsuo-Wen Lu , I-Ming Lai , Tsung-Yu Hou , Chien-Liang Lin , Wen-Yi Teng , Shao-Wei Wang , Yu-Ren Wang , Chin-Cheng Chien
IPC分类号: H01L21/20
CPC分类号: H01L21/0243 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02658 , H01L29/165 , H01L29/66636 , H01L29/7834
摘要: A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.
摘要翻译: 制造外延层的方法包括提供衬底。 衬底被蚀刻以在衬底内形成至少一个凹部。 在凹部上进行表面处理以形成含Si-OH的表面。 进行原位外延工艺以在凹槽内形成外延层,其中外延工艺在无氢气氛和低于800℃的温度下进行。
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公开(公告)号:US20120270382A1
公开(公告)日:2012-10-25
申请号:US13091153
申请日:2011-04-21
申请人: Tsuo-Wen Lu , I-Ming Lai , Tsung-Yu Hou , Chien-Liang Lin , Wen-Yi Teng , Shao-Wei Wang , Yu-Ren Wang , Chin-Cheng Chien
发明人: Tsuo-Wen Lu , I-Ming Lai , Tsung-Yu Hou , Chien-Liang Lin , Wen-Yi Teng , Shao-Wei Wang , Yu-Ren Wang , Chin-Cheng Chien
IPC分类号: H01L21/20
CPC分类号: H01L21/0243 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02658 , H01L29/165 , H01L29/66636 , H01L29/7834
摘要: A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.
摘要翻译: 制造外延层的方法包括提供衬底。 衬底被蚀刻以在衬底内形成至少一个凹部。 在凹部上进行表面处理以形成含Si-OH表面。 进行原位外延工艺以在凹槽内形成外延层,其中外延工艺在无氢气氛和低于800℃的温度下进行。
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公开(公告)号:US08536038B2
公开(公告)日:2013-09-17
申请号:US13164781
申请日:2011-06-21
申请人: Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen , Yu-Min Lin , Chin-Cheng Chien , Jei-Ming Chen , Chun-Wei Hsu , Chia-Lung Chang , Yi-Ching Wu , Shu-Yen Chan
发明人: Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen , Yu-Min Lin , Chin-Cheng Chien , Jei-Ming Chen , Chun-Wei Hsu , Chia-Lung Chang , Yi-Ching Wu , Shu-Yen Chan
IPC分类号: H01L21/3205 , H01L21/425
CPC分类号: H01L29/7833 , H01L21/265 , H01L21/3215 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.
摘要翻译: 一种金属栅极的制造方法,包括提供具有至少形成有导电类型的半导体器件的衬底,在该半导体器件中形成栅极沟槽,形成具有导电类型的功函数金属层和对应于 栅极沟槽中的导电类型,并且执行离子注入以将功函数金属层的固有功函数调整到目标功函数。
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公开(公告)号:US20120329261A1
公开(公告)日:2012-12-27
申请号:US13164781
申请日:2011-06-21
申请人: Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen , Yu-Min Lin , Chin-Cheng Chien , Jei-Ming Chen , Chun-Wei Hsu , Chia-Lung Chang , Yi-Ching Wu , Shu-Yen Chan
发明人: Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen , Yu-Min Lin , Chin-Cheng Chien , Jei-Ming Chen , Chun-Wei Hsu , Chia-Lung Chang , Yi-Ching Wu , Shu-Yen Chan
IPC分类号: H01L21/782 , H01L21/28
CPC分类号: H01L29/7833 , H01L21/265 , H01L21/3215 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.
摘要翻译: 一种金属栅极的制造方法,包括提供具有至少形成有导电类型的半导体器件的衬底,在该半导体器件中形成栅极沟槽,形成具有导电类型的功函数金属层和对应于 栅极沟槽中的导电类型,并且执行离子注入以将功函数金属层的固有功函数调整到目标功函数。
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公开(公告)号:US08921238B2
公开(公告)日:2014-12-30
申请号:US13235515
申请日:2011-09-19
申请人: Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen
发明人: Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen
IPC分类号: H01L21/31 , H01L21/3105 , H01L21/02
CPC分类号: H01L21/3105 , H01L21/02148 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02192 , H01L21/02197 , H01L21/0228
摘要: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.
摘要翻译: 一种用于处理高k电介质层的方法包括以下步骤。 提供半导体衬底,并且在其上形成高k电介质层。 高k电介质层具有结晶温度。 随后,进行第一退火处理,并且第一退火工艺的处理温度显着小于结晶温度。 进行第二退火处理,第二退火处理的工艺温度显着大于结晶温度。
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公开(公告)号:US20130072030A1
公开(公告)日:2013-03-21
申请号:US13235515
申请日:2011-09-19
申请人: Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen
发明人: Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen
IPC分类号: H01L21/314
CPC分类号: H01L21/3105 , H01L21/02148 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02192 , H01L21/02197 , H01L21/0228
摘要: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.
摘要翻译: 一种用于处理高k电介质层的方法包括以下步骤。 提供半导体衬底,并且在其上形成高k电介质层。 高k电介质层具有结晶温度。 随后,进行第一退火处理,并且第一退火工艺的处理温度显着小于结晶温度。 进行第二退火处理,第二退火处理的工艺温度显着大于结晶温度。
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公开(公告)号:US20120309171A1
公开(公告)日:2012-12-06
申请号:US13118473
申请日:2011-05-30
申请人: Tsuo-Wen Lu , Wen-Yi Teng , Yu-Ren Wang , Gin-Chen Huang , Chien-Liang Lin , Shao-Wei Wang , Ying-Wei Yen , Ya-Chi Cheng , Shu-Yen Chan , Chan-Lon Yang
发明人: Tsuo-Wen Lu , Wen-Yi Teng , Yu-Ren Wang , Gin-Chen Huang , Chien-Liang Lin , Shao-Wei Wang , Ying-Wei Yen , Ya-Chi Cheng , Shu-Yen Chan , Chan-Lon Yang
IPC分类号: H01L21/20
CPC分类号: H01L29/6656 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer.
摘要翻译: 公开了半导体器件的制造方法。 该方法包括以下步骤:提供衬底,其中衬底包括其上的栅极结构; 在所述衬底上形成膜叠层并覆盖所述栅极结构,其中所述膜堆叠至少包括氧化物层和氮化物层; 移除所述薄膜叠层的一部分以形成邻近所述栅极结构的两侧的凹槽和所述栅极结构侧壁上的一次性间隔物; 并用包含硅原子的材料填充凹部,以形成刻面材料层。
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公开(公告)号:US20120228723A1
公开(公告)日:2012-09-13
申请号:US13045291
申请日:2011-03-10
申请人: Shao-Wei Wang , Gin-Chen Huang , Tsuo-Wen Lu , Chien-Liang Lin , Yu-Ren Wang
发明人: Shao-Wei Wang , Gin-Chen Huang , Tsuo-Wen Lu , Chien-Liang Lin , Yu-Ren Wang
IPC分类号: H01L29/772 , H01L21/28
CPC分类号: H01L29/513 , H01L21/28185 , H01L21/28202 , H01L29/518
摘要: A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.
摘要翻译: 对栅极结构及其制造方法进行说明。 提供衬底,并且在衬底上形成栅极电介质层。 栅电介质层的形成包括通过同时引入含氮气体和含硅气体在衬底上沉积氮化硅层。 栅极形成在栅极介电层上,以形成栅极结构。
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公开(公告)号:US08501634B2
公开(公告)日:2013-08-06
申请号:US13045291
申请日:2011-03-10
申请人: Shao-Wei Wang , Gin-Chen Huang , Tsuo-Wen Lu , Chien-Liang Lin , Yu-Ren Wang
发明人: Shao-Wei Wang , Gin-Chen Huang , Tsuo-Wen Lu , Chien-Liang Lin , Yu-Ren Wang
IPC分类号: H01L21/31
CPC分类号: H01L29/513 , H01L21/28185 , H01L21/28202 , H01L29/518
摘要: A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.
摘要翻译: 对栅极结构及其制造方法进行说明。 提供衬底,并且在衬底上形成栅极电介质层。 栅电介质层的形成包括通过同时引入含氮气体和含硅气体在衬底上沉积氮化硅层。 栅极形成在栅极介电层上,以形成栅极结构。
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公开(公告)号:US20120292720A1
公开(公告)日:2012-11-22
申请号:US13109999
申请日:2011-05-18
申请人: Chih-Chung Chen , Yu-Ren Wang , Tsuo-Wen Lu , Wen-Yi Teng
发明人: Chih-Chung Chen , Yu-Ren Wang , Tsuo-Wen Lu , Wen-Yi Teng
IPC分类号: H01L29/772 , H01L21/336
CPC分类号: H01L29/4983 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要: A metal gate structure includes a high dielectric constant (high-K) gate dielectric layer, a metal gate having at least a U-shaped work function metal layer positioned on the high-K gate dielectric layer, and a silicon carbonitride (SiCN) seal layer positioned on sidewalls of the high-K gate dielectric layer and of the metal gate.
摘要翻译: 金属栅极结构包括高介电常数(高K)栅极电介质层,至少具有位于高K栅极介电层上的U形功函数金属层的金属栅极和碳氮化硅(SiCN)密封 层位于高K栅极电介质层和金属栅极的侧壁上。
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