公开(公告)号：US08299498B2

公开(公告)日：2012-10-30

申请号：US12595253

申请日：2008-04-07

申请人： Tsutomu Uesugi ,  Kenji Ito ,  Osamu Ishiguro ,  Tetsu Kachi ,  Masahiro Sugimoto

发明人： Tsutomu Uesugi ,  Kenji Ito ,  Osamu Ishiguro ,  Tetsu Kachi ,  Masahiro Sugimoto

IPC分类号： H01L29/66

CPC分类号： H01L29/2003 ,  H01L29/045 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7828

摘要： A semiconductor device 10 is provided with a first hetero junction 40b configured with two types of nitride semiconductors having different bandgap energy from each other, a second hetero junction 50b configured with two types of nitride semiconductors having different bandgap energy from each other, and a gate electrode 58 facing the second hetero junction 50b. The second hetero junction 50b is configured to be electrically connected to the first hetero junction 40b. The first hetero junction 40b is a c-plane and the second hetero junction 50b is either an a-plane or an m-plane.

摘要翻译： 半导体器件10设置有由彼此具有不同带隙能量的两种类型的氮化物半导体构成的第一异质结40b，由具有彼此具有不同带隙能量的两种类型的氮化物半导体构成的第二异质结50b，以及栅极 电极58面对第二异质结50b。 第二异质结50b被配置为电连接到第一异质结40b。 第一异质结40b是c面，第二异质结50b是a面或m面。

公开(公告)号：US20100117119A1

公开(公告)日：2010-05-13

申请号：US12595253

申请日：2008-04-07

申请人： Tsutomu Uesugi ,  Kenji Ito ,  Osamu Ishiguro ,  Tetsu Kachi ,  Masahiro Sugimoto

发明人： Tsutomu Uesugi ,  Kenji Ito ,  Osamu Ishiguro ,  Tetsu Kachi ,  Masahiro Sugimoto

IPC分类号： H01L29/778

CPC分类号： H01L29/2003 ,  H01L29/045 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7828

摘要： A semiconductor device 10 is provided with a first hetero junction 40b configured with two types of nitride semiconductors having different bandgap energy from each other, a second hetero junction 50b configured with two types of nitride semiconductors having different bandgap energy from each other, and a gate electrode 58 facing the second hetero junction 50b. The second hetero junction 50b is configured to be electrically connected to the first hetero junction 40b. The first hetero junction 40b is a c-plane and the second hetero junction 50b is either an a-plane or an m-plane.

摘要翻译： 半导体器件10设置有由彼此具有不同带隙能量的两种类型的氮化物半导体构成的第一异质结40b，由具有彼此具有不同带隙能量的两种类型的氮化物半导体构成的第二异质结50b，以及栅极 电极58面对第二异质结50b。 第二异质结50b被配置为电连接到第一异质结40b。 第一异质结40b是c面，第二异质结50b是a面或m面。

公开(公告)号：US20080090395A1

公开(公告)日：2008-04-17

申请号：US11902087

申请日：2007-09-19

申请人： Masahiro Sugimoto ,  Masakazu Kanechika ,  Daigo Kikuta ,  Osamu Ishiguro ,  Tsutomu Uesugi ,  Tetsu Kachi

发明人： Masahiro Sugimoto ,  Masakazu Kanechika ,  Daigo Kikuta ,  Osamu Ishiguro ,  Tsutomu Uesugi ,  Tetsu Kachi

IPC分类号： H01L21/225

CPC分类号： H01L21/2258 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/7828 ,  H01L29/808 ,  H01L29/861 ,  H01L33/325

摘要： The present invention provides a p-type group III nitride semiconductor production method which is excellent in terms of reliability and reproducibility. A photoresist mask is formed on a surface of an n−-GaN layer. Subsequently, an Mg film is formed so as to cover the n−-GaN layer and the photoresist mask, and an Ni/Pt metal film is formed on the Mg film. Thereafter, the photoresist mask is removed, whereby the Mg film and the metal film remain only on a portion of the n−-GaN layer where a p-type region is formed. Subsequently, when thermal treatment is performed in an ammonia atmosphere at 900° C. for three hours, Mg is diffused in the n−-GaN layer while being activated. Therefore, a p-type region is formed. Thereafter, the Mg film and the metal film are removed by use of aqua regia.

摘要翻译： 本发明提供了可靠性和再现性优异的p型III族氮化物半导体制造方法。 光刻胶掩模形成在n + O-GaN层的表面上。 随后，形成Mg膜，以覆盖n + SUP-GaN层和光致抗蚀剂掩模，并且在Mg膜上形成Ni / Pt金属膜。 此后，除去光致抗蚀剂掩模，由此Mg膜和金属膜仅保留在形成p型区域的n + O - GaN层的一部分上。 随后，当在900℃的氨气氛中进行3小时的热处理时，Mg在被激活的同时在n + SUP-GaN层中扩散。 因此，形成p型区域。 此后，通过使用王水去除Mg膜和金属膜。

公开(公告)号：US08188514B2

公开(公告)日：2012-05-29

申请号：US12540230

申请日：2009-08-12

申请人： Masahiro Sugimoto ,  Tat-Sing Paul Chow ,  Zhongda Li ,  Tetsu Kachi ,  Tsutomu Uesugi

发明人： Masahiro Sugimoto ,  Tat-Sing Paul Chow ,  Zhongda Li ,  Tetsu Kachi ,  Tsutomu Uesugi

IPC分类号： H01L29/66

CPC分类号： H01L29/7787 ,  H01L29/0642 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7788

摘要： An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.

摘要翻译： 公开了一种HEMT型晶体管，其是常闭型，栅极阈值电压的变化小。 晶体管设置有p型区域，势垒区域，绝缘膜，栅极电极。 沟道区域连接到p型区域的上表面。 通道区域是n型或i型，并且设置有第一通道区域和第二通道区域。 阻挡区域与第一通道区域的上表面形成异质结。 绝缘膜连接到第二通道区域的上表面和阻挡区域的上表面。 栅电极经由绝缘膜面向第二沟道区和阻挡区。 第一通道区域和第二通道区域在电流通路中串联布置。

公开(公告)号：US20090134456A1

公开(公告)日：2009-05-28

申请号：US11921085

申请日：2006-05-25

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/207 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7828 ,  H01L29/7832

摘要： The present invention aims to suppress the diffusion of p-type impurities (typically magnesium), included in a semiconductor region of a III-V compound semiconductor, into an adjoining different semiconductor region. A semiconductor device 10 of the present invention comprises a first semiconductor region 28 of gallium nitride (GaN) including p-type impurities that consist of magnesium, a second semiconductor region 34 of gallium nitride, and an impurity diffusion suppression layer 32 of silicon oxide (SiO2) located between the first semiconductor region 28 and the second semiconductor region 34.

摘要翻译： 本发明旨在抑制包含在III-V族化合物半导体的半导体区域中的p型杂质（通常为镁）扩散到邻接的不同半导体区域中。 本发明的半导体器件10包括由镁构成的p型杂质，氮化镓的第二半导体区域34和氧化硅的杂质扩散抑制层32的氮化镓（GaN）的第一半导体区域28（ SiO 2），位于第一半导体区域28和第二半导体区域34之间。

公开(公告)号：US07777252B2

公开(公告)日：2010-08-17

申请号：US11632665

申请日：2005-06-22

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/739 ,  H01L31/072

CPC分类号： H01L29/778 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

摘要翻译： 半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。 此外，SI-GaN层的杂质浓度小于1×1017cm-3。 包括III-V半导体的半导体器件可以具有稳定的常关断操作。

公开(公告)号：US09184271B2

公开(公告)日：2015-11-10

申请号：US12822328

申请日：2010-06-24

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L21/28 ,  H01L29/20

CPC分类号： H01L29/778 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

摘要翻译： 半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。 此外，SI-GaN层的杂质浓度小于1×1017cm-3。 包括III-V半导体的半导体器件可以具有稳定的常关断操作。

公开(公告)号：US20100044753A1

公开(公告)日：2010-02-25

申请号：US12544451

申请日：2009-08-20

申请人： Masahiro SUGIMOTO ,  Hiroyuki Ueda ,  Tsutomu Uesugi ,  Masakazu Kanechika ,  Tetsu Kachi

发明人： Masahiro SUGIMOTO ,  Hiroyuki Ueda ,  Tsutomu Uesugi ,  Masakazu Kanechika ,  Tetsu Kachi

IPC分类号： H01L29/205 ,  H01L29/78

CPC分类号： H01L29/2003 ,  H01L21/28264 ,  H01L29/41766 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7787 ,  H01L29/7788

摘要： A nitride semiconductor device 2 comprises a nitride semiconductor layer 10. A gate insulating film 16 is formed on the surface of the nitride semiconductor layer 10. The gate insulating film 16 includes a portion composed of an aluminum nitride film 15 and a portion composed of an insulating material 14 that contains at least one of oxygen or silicon. A region W2 of the nitride semiconductor layer 10 facing the aluminum nitride film 15 is included in a region W1 of the nitride semiconductor layer 10 facing a gate electrode 18. The nitride semiconductor device 2 may further comprise a nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may be stacked on the surface of the nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may have a larger band gap than that of the nitride semiconductor lower layer 8 and have a heterojunction formed there between.

摘要翻译： 氮化物半导体器件2包括氮化物半导体层10.栅极绝缘膜16形成在氮化物半导体层10的表面上。栅极绝缘膜16包括由氮化铝膜15构成的部分和由 包含氧或硅中的至少一种的绝缘材料14。 面向氮化铝膜15的氮化物半导体层10的区域W2包含在氮化物半导体层10的面向栅极电极18的区域W1中。氮化物半导体器件2还可以包括氮化物半导体下层8.氮化物半导体层 半导体层10可以堆叠在氮化物半导体下层8的表面上。氮化物半导体层10可以具有比氮化物半导体下层8更大的带隙，并且在其间形成异质结。

公开(公告)号：US20080149964A1

公开(公告)日：2008-06-26

申请号：US11795117

申请日：2006-01-20

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/778

CPC分类号： H01L29/452 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.

摘要翻译： 半导体器件10包括由p型氮化镓制成的下半导体层26和由n型AlGaN制成的上半导体层28之间的异质结，其中上半导体层28具有比下半导体层26更大的带隙 。 半导体器件10还包括形成在上半导体层28的顶表面的一部分上的漏电极32，形成在上半导体层28的顶表面的不同部分上的源极34和栅电极36 电连接到下半导体层26。 半导体器件10可以正常工作。

公开(公告)号：US20080128862A1

公开(公告)日：2008-06-05

申请号：US11667735

申请日：2005-11-14

申请人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

发明人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

IPC分类号： H01L21/20 ,  H01L29/20

CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/41 ,  H01L29/778 ,  H01L29/7788 ,  H01L29/8122

摘要： A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

摘要翻译： 半导体器件设置有漏电极22，半导体基板32，覆盖半导体基板32的一部分表面的电流调节层42，并在半导体基板的表面留下未被覆盖的表面55 板32，覆盖电流调节层42的表面的半导体层50和形成在半导体层50的表面的源电极62。 在半导体层50内形成有漂移区56，沟道形成区54和源极区52。 漏电极22连接到电源的第一端子，源电极62连接到电源的第二端子。 利用该半导体层50，可以提高耐压或减少电流泄漏的发生。