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公开(公告)号：US08314658B2
公开(公告)日：2012-11-20
申请号：US12882592
申请日：2010-09-15
IPC分类号： H03F3/68
CPC分类号： H03F3/45076 , H03F3/19 , H03F3/211 , H03F3/602 , H03F2200/537 , H03F2200/541 , H03F2203/45731
摘要： A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.
摘要翻译： 功率放大器包括设置在整体上呈圆形几何形状的基板上的多个初级电感器; 多个放大器对; 次级电感; 和连接线。 每个放大器对耦合到相应的初级电感器的两端，并且分别放大并输出到相应的初级电感器作为差分输入信号给出的一对第一和第二信号。 次级电感器以圆形几何形状邻近初级电感器提供，进一步组合并输出通过在每个初级电感器中组合第一和第二信号而产生的信号。 连接布线设置在基板上的主电感器的内部，并且将各个初级电感器的中点彼此电耦合。
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公开(公告)号：US08330544B2
公开(公告)日：2012-12-11
申请号：US13367121
申请日：2012-02-06
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Satoshi Yamakawa , Tetsuya Iida , Masao Kondo , Yutaka Hoshino
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Satoshi Yamakawa , Tetsuya Iida , Masao Kondo , Yutaka Hoshino
IPC分类号： H03F3/26
CPC分类号： H03F3/211 , H03F1/56 , H03F3/26 , H03F2200/537 , H03F2203/21139
摘要： In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
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公开(公告)号：US08493152B2
公开(公告)日：2013-07-23
申请号：US13621096
申请日：2012-09-15
IPC分类号： H03F3/68
CPC分类号： H03F3/45076 , H03F3/19 , H03F3/211 , H03F3/602 , H03F2200/537 , H03F2200/541 , H03F2203/45731
摘要： A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.
摘要翻译： 功率放大器包括设置在整体上呈圆形几何形状的基板上的多个初级电感器; 多个放大器对; 次级电感; 和连接线。 每个放大器对耦合到相应的初级电感器的两端，并且分别放大并输出到相应的初级电感器作为差分输入信号给出的一对第一和第二信号。 次级电感器以圆形几何形状邻近初级电感器提供，进一步组合并输出通过在每个初级电感器中组合第一和第二信号而产生的信号。 连接布线设置在基板上的主电感器的内部，并且将各个初级电感器的中点彼此电耦合。
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公开(公告)号：US08134408B2
公开(公告)日：2012-03-13
申请号：US12617488
申请日：2009-11-12
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Satoshi Yamakawa , Tetsuya Iida , Masao Kondo , Yutaka Hoshino
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Satoshi Yamakawa , Tetsuya Iida , Masao Kondo , Yutaka Hoshino
IPC分类号： H03F3/26
CPC分类号： H03F3/211 , H03F1/56 , H03F3/26 , H03F2200/537 , H03F2203/21139
摘要： In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
摘要翻译： 为了实现功率放大电路的频率特性的更宽的带宽，通过二次电感器将分别以不同频率匹配的差分推挽放大器的输出组合在一起，并且输出组合信号。
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公开(公告)号：US08093950B2
公开(公告)日：2012-01-10
申请号：US12622034
申请日：2009-11-19
IPC分类号： H03F3/45
CPC分类号： H03F3/26 , H03F3/211 , H03F3/45188 , H03F2203/45731
摘要： A power amplifier amplifying and compositing differential signals and capable of suppressing harmonics is provided. The power amplifier includes first amplifiers amplifying a first input signal and a second input signal, which are differential signals, a first coil receiving the first input signal and the second input signal amplified by the first amplifiers, a second coil magnetically coupled with the first coil and outputting a composite signal of the amplified first input signal and second input signal, a third coil magnetically coupled with the second coil, and a first capacitor coupled between both ends of the third coil, wherein one end of the first capacitor is coupled to a ground node.
摘要翻译： 提供功率放大和合成差分信号并能够抑制谐波。 功率放大器包括放大作为差分信号的第一输入信号和第二输入信号的第一放大器，接收由第一放大器放大的第一输入信号和第二输入信号的第一线圈，与第一线圈磁耦合的第二线圈 并输出放大的第一输入信号和第二输入信号的复合信号，与第二线圈磁耦合的第三线圈，以及耦合在第三线圈两端之间的第一电容器，其中第一电容器的一端耦合到 接地节点。
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公开(公告)号：US20100148872A1
公开(公告)日：2010-06-17
申请号：US12622034
申请日：2009-11-19
IPC分类号： H03F3/26
CPC分类号： H03F3/26 , H03F3/211 , H03F3/45188 , H03F2203/45731
摘要： A power amplifier amplifying and compositing differential signals and capable of suppressing harmonics is provided. The power amplifier includes first amplifiers amplifying a first input signal and a second input signal, which are differential signals, a first coil receiving the first input signal and the second input signal amplified by the first amplifiers, a second coil magnetically coupled with the first coil and outputting a composite signal of the amplified first input signal and second input signal, a third coil magnetically coupled with the second coil, and a first capacitor coupled between both ends of the third coil, wherein one end of the first capacitor is coupled to a ground node.
摘要翻译： 提供功率放大和合成差分信号并能够抑制谐波。 功率放大器包括放大作为差分信号的第一输入信号和第二输入信号的第一放大器，接收由第一放大器放大的第一输入信号和第二输入信号的第一线圈，与第一线圈磁耦合的第二线圈 并输出放大的第一输入信号和第二输入信号的复合信号，与第二线圈磁耦合的第三线圈，以及耦合在第三线圈两端之间的第一电容器，其中第一电容器的一端耦合到 接地节点。
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公开(公告)号：US20140203393A1
公开(公告)日：2014-07-24
申请号：US14239375
申请日：2012-07-31
申请人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
发明人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
IPC分类号： H01L29/872
CPC分类号： H01L29/8725 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/8611 , H01L29/872
摘要： A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.
摘要翻译： 具有高击穿电压和高可靠性的半导体器件，而不形成具有高定位精度的嵌入式注入层。 半导体器件包括形成在第一导电类型的半导体层的表面层上的第二导电类型的有源区的基底，以构成半导体元件; 保护环作为多个第一导电类型的第一杂质区域，形成在半导体层的表面层上彼此间隔开以在平面图中分别包围基底; 以及作为第二导电类型的第二杂质区域的嵌入式注入层，其嵌入在半导体层的表面层中，以连接多个保护环的至少两个底部。
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公开(公告)号：US09202940B2
公开(公告)日：2015-12-01
申请号：US14239375
申请日：2012-07-31
申请人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
发明人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
IPC分类号： H01L29/06 , H01L29/872 , H01L29/861 , H01L29/16
CPC分类号： H01L29/8725 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/8611 , H01L29/872
摘要： A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.
摘要翻译： 具有高击穿电压和高可靠性的半导体器件，而不形成具有高定位精度的嵌入式注入层。 半导体器件包括形成在第一导电类型的半导体层的表面层上的第二导电类型的有源区的基底，以构成半导体元件; 保护环作为多个第一导电类型的第一杂质区域，形成在半导体层的表面层上彼此间隔开以在平面图中分别包围基底; 以及作为第二导电类型的第二杂质区域的嵌入式注入层，其嵌入在半导体层的表面层中，以连接多个保护环的至少两个底部。
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公开(公告)号：US20140353678A1
公开(公告)日：2014-12-04
申请号：US14363914
申请日：2012-08-02
IPC分类号： H01L29/06 , H01L29/66 , H01L29/861 , H01L29/78 , H01L21/266 , H01L29/872
CPC分类号： H01L29/063 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0692 , H01L29/0847 , H01L29/1608 , H01L29/42368 , H01L29/66136 , H01L29/66143 , H01L29/66659 , H01L29/7835 , H01L29/8611 , H01L29/872
摘要： A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region.
摘要翻译： 半导体器件包括形成在第一导电类型的半导体层的上层部分中的有源区和从有源区的边缘朝向外部设置以围绕有源区的多个电场弛豫层。 多个电场弛豫层包括彼此相邻交替设置的多个第一电场弛豫层和多个第二电场弛豫层，第一电场弛豫层和彼此相邻的第二电场弛豫层形成 一套。 第二导电类型的杂质以第一表面密度注入第一电场弛豫层，其宽度随着活性区域的变小而变小。 第二导电类型的杂质以比第一表面密度低的第二表面密度注入第二电场弛豫层，其宽度随着活性区域的变大而变大。
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公开(公告)号：US20130140582A1
公开(公告)日：2013-06-06
申请号：US13816511
申请日：2011-04-15
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
IPC分类号： H01L29/12 , H01L21/265
CPC分类号： H01L29/12 , H01L21/0465 , H01L21/265 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/66128 , H01L29/66143 , H01L29/66659 , H01L29/7835 , H01L29/8611 , H01L29/872
摘要： The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (101) including a plurality of P-type implantation layers having a relatively low concentration of P-type impurity is formed adjacent to an active region (2). The RESURF layer (101) includes a first RESURF layer (11), a second RESURF layer (12), a third RESURF layer (13), a fourth RESURF layer (14), and a fifth RESURF layer (15) that are arranged sequentially from the P-type base (2) side so as to surround the P-type base (2). The second RESURF layer (12) is configured with small regions (11′) having an implantation amount equal to that of the first RESURF layer (11) and small regions (13′) having an implantation amount equal to that of the third RESURF layer (13) being alternately arranged in multiple. The fourth RESURF layer (14) is configured with small regions (13′) having an implantation amount equal to that of the third RESURF layer (13) and small regions (15′) having an implantation amount equal to that of the fifth RESURF layer (15) being alternately arranged in multiple.
摘要翻译： 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 在活性区域（2）附近形成包括具有相对低浓度的P型杂质的多个P型注入层的RESURF层（101）。 RESURF层（101）包括第一RESURF层（11），第二RESURF层（12），第三RESURF层（13），第四RESURF层（14）和第五RESURF层（15） 从P型基底（2）侧顺序地包围P型基底（2）。 第二RESURF层（12）配置有具有等于第一RESURF层（11）的注入量的小区域（11'）和具有等于第三RESURF层的注入量的小区域（13'） （13）交替布置成多个。 第四RESURF层（14）配置有具有等于第三RESURF层（13）的注入量的小区域（13'）和具有等于第五RESURF层的注入量的小区域（15'） （15）交替排列成多个。
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