公开(公告)号：US09748386B2

公开(公告)日：2017-08-29

申请号：US14922215

申请日：2015-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-cheng Hu ,  Tien-I Wu ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: An epitaxial structure of semiconductor device includes a substrate, a recess, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The recess is formed in the substrate and disposed near a surface of the substrate, wherein the recess has a recess depth. The first epitaxial layer is disposed on surfaces of a sidewall and a bottom of the recess. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein the Ge concentration of the second epitaxial layer is greater than the Ge concentration of the first epitaxial layer. The third epitaxial layer is disposed on the surface of the second epitaxial layer, wherein the Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer, and the depth of the third epitaxial layer is about ½ to about ¾ of the recess depth.

公开(公告)号：US09741818B2

公开(公告)日：2017-08-22

申请号：US14964546

申请日：2015-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Yu-Ying Lin ,  I-cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Yu-Ren Wang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324

CPC classification number: H01L21/02587 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.

公开(公告)号：US20170170296A1

公开(公告)日：2017-06-15

申请号：US14964546

申请日：2015-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Yu-Ying Lin ,  I-cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Yu-Ren Wang

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/02587 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.

公开(公告)号：US20170133460A1

公开(公告)日：2017-05-11

申请号：US14936651

申请日：2015-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-I Wu ,  I-cheng Hu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Kun-Hsin Chen ,  Neng-Hui Yang ,  Shu-Yen Chan

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/16 ,  H01L21/283 ,  H01L29/423 ,  H01L21/306 ,  H01L21/225

CPC classification number: H01L21/283 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, including: first, a substrate is provided. Next, at least two gate structures are formed on the substrate, each gate structure including two spacers disposed on two sides of the gate structure. Afterwards, a dry etching process is performed to remove parts of the substrate, so as to form a recess in the substrate, and a wet etching process is performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively. In addition, parts of the spacer are also removed through the wet etching process, and each spacer includes a rounding corner disposed on a bottom surface of the spacer.

公开(公告)号：US20170117410A1

公开(公告)日：2017-04-27

申请号：US14922215

申请日：2015-10-26

Applicant: United Microelectronics Corp.

Inventor： I-cheng Hu ,  Tien-I Wu ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: An epitaxial structure of semiconductor device includes a substrate, a recess, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The recess is formed in the substrate and disposed near a surface of the substrate, wherein the recess has a recess depth. The first epitaxial layer is disposed on surfaces of a sidewall and a bottom of the recess. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein the Ge concentration of the second epitaxial layer is greater than the Ge concentration of the first epitaxial layer. The third epitaxial layer is disposed on the surface of the second epitaxial layer, wherein the Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer, and the depth of the third epitaxial layer is about ½ to about ¾ of the recess depth.