公开(公告)号：US09583641B1

公开(公告)日：2017-02-28

申请号：US14960453

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Chih-Chien Chang ,  Jianjun Yang ,  Wen-Chuan Chang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7923 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66833

Abstract: A manufacturing method of a semiconductor device includes the following steps. A plurality of select gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between the two adjacent select gates. An insulation block is formed between the two charge storage structures and formed on the source region. A memory gate is formed on the insulation block, and the memory gate is connected to the two charge storage structures.

Abstract translation: 半导体器件的制造方法包括以下步骤。 多个选择栅极形成在半导体衬底的存储区域上。 在两个相邻的选择门之间形成两个电荷存储结构。 源区域形成在半导体衬底中，并且源区域形成在两个相邻的选择栅极之间。 在两个电荷存储结构之间形成绝缘块并形成在源极区上。 存储器栅极形成在绝缘块上，并且存储器栅极连接到两个电荷存储结构。

公开(公告)号：US20170338239A1

公开(公告)日：2017-11-23

申请号：US15161419

申请日：2016-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Wang Xiang ,  Yi-Shan Chiu

IPC: H01L27/11582 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L29/40117 ,  H01L29/4234

Abstract: A semiconductor structure includes a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes a gate structure. The gate structures are spaced from each other by a spacing S. Each gate structure includes a dielectric layer and a gate electrode. The dielectric layer has an U-shape and defines an opening toward upside. The gate electrode is disposed in the opening. Each gate structure has a length L. A ratio of S/L is smaller than 1.

公开(公告)号：US20150270277A1

公开(公告)日：2015-09-24

申请号：US14220122

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  ZHEN CHEN ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Wei Ta

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract translation: 本发明提供了一种存储单元，其包括基板，栅极介电层，图案化材料层，选择栅极和控制栅极。 栅介电层设置在基板上。 图案化材料层设置在基底上，其中图案化材料层包括垂直部分和水平部分。 选择栅极设置在栅极电介质层和图案化材料层的垂直部分的一侧。 控制栅极设置在图案化材料层的水平部分上并且在垂直部分的另一侧，其中垂直部分在选择栅极的顶部上方突出。 本发明还提供了存储单元的另一实施例及其制造方法。

公开(公告)号：US20160049525A1

公开(公告)日：2016-02-18

申请号：US14462550

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Abstract translation: 闪速存储器结构包括衬底上的存储栅极，与存储栅极相邻的选择栅极以及存储栅极和选择栅极之间的氧化物氮化物间隔物，其中氧化物氮化物间隔物还包括氧化物层和氮化物 层具有上部氮化物部分和下部氮化物部分，并且上部氮化物部分比下部氮化物部分薄。

公开(公告)号：US09111796B2

公开(公告)日：2015-08-18

申请号：US14158875

申请日：2014-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhen Chen ,  Shen-De Wang ,  Yi-Shan Chiu ,  Wei Cheng

IPC: H01L27/115 ,  H01L23/00 ,  H01L27/02 ,  H01L27/105

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11524

Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

Abstract translation: 用于存储器件的布局结构包括多个第一栅极图案，多个第一着陆焊盘图案，多个虚设图案，多个第二着陆焊盘图案和多个第二栅极图案。 第一着陆焊盘图案彼此平行并电连接到第一栅极图案。 交替布置虚拟图案和第一着陆焊盘图案，并且第二着陆焊盘图案分别位于一个第一着陆焊盘图案和一个虚设图案之间。 第二栅极图案电连接到第二着陆焊盘图案。

公开(公告)号：US09660106B2

公开(公告)日：2017-05-23

申请号：US14462550

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

公开(公告)号：US20160172200A1

公开(公告)日：2016-06-16

申请号：US14569794

申请日：2014-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WEICHANG LIU ,  ZHEN CHEN ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang ,  Chih-Chien Chang

IPC: H01L21/28

CPC classification number: H01L29/40117 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating non-volatile memory device is disclosed. The method includes the steps of: providing a substrate having a stack structure thereon; performing a first oxidation process to form a first oxide layer on the substrate and the stack structure; etching the first oxide layer for forming a first spacer adjacent to the stack structure; performing a second oxidation process to form a second oxide layer on the substrate; forming a dielectric layer on the first spacer and the second oxide layer; and etching the dielectric layer for forming a second spacer.

Abstract translation: 公开了一种用于制造非易失性存储器件的方法。 该方法包括以下步骤：提供其上具有堆叠结构的衬底; 执行第一氧化工艺以在衬底和堆叠结构上形成第一氧化物层; 蚀刻用于形成邻近堆叠结构的第一间隔物的第一氧化物层; 执行第二氧化工艺以在所述衬底上形成第二氧化物层; 在所述第一间隔物和所述第二氧化物层上形成介电层; 并蚀刻用于形成第二间隔物的电介质层。

公开(公告)号：US20160042957A1

公开(公告)日：2016-02-11

申请号：US14454332

申请日：2014-08-07

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。

公开(公告)号：US10020385B2

公开(公告)日：2018-07-10

申请号：US14220122

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Zhen Chen ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  Jianjun Yang ,  Wei Ta

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

公开(公告)号：US09748256B2

公开(公告)日：2017-08-29

申请号：US14924525

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Yi-Shan Chiu ,  Wei Ta

IPC: H01L29/788 ,  H01L27/11524 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.