公开(公告)号：US10332978B2

公开(公告)日：2019-06-25

申请号：US15689780

申请日：2017-08-29

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chia-Lin Lu ,  Yu-Cheng Tung ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/768

Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

公开(公告)号：US09978854B2

公开(公告)日：2018-05-22

申请号：US15156351

申请日：2016-05-17

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Jhen-Cyuan Li ,  Shui-Yen Lu ,  Man-Ling Lu ,  Yu-Cheng Tung ,  Chung-Fu Chang

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/30 ,  H01L21/82 ,  H01L27/088 ,  H01L29/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/7848

Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.

公开(公告)号：US20170117380A1

公开(公告)日：2017-04-27

申请号：US14924479

申请日：2015-10-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chia-Lin Lu ,  Yu-Cheng Tung ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

公开(公告)号：US20180006133A1

公开(公告)日：2018-01-04

申请号：US15689780

申请日：2017-08-29

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chia-Lin Liu ,  Yu-Cheng Tung ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

公开(公告)号：US09780193B2

公开(公告)日：2017-10-03

申请号：US14924479

申请日：2015-10-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chia-Lin Lu ,  Yu-Cheng Tung ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

公开(公告)号：US09443970B2

公开(公告)日：2016-09-13

申请号：US14924734

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hsin-Ming Hou ,  Yu-Cheng Tung ,  Ji-Fu Kung ,  Wai-Yi Lien ,  Ming-Tsung Chen

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/76224 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.

Abstract translation: 提供了包括衬底，多个隔离结构，至少栅极结构，多个虚拟栅极结构和多个外延结构的半导体器件。 衬底具有由设置在衬底内的隔离结构限定的有源区域。 也就是说，在隔离结构之间限定有源区。 栅极结构设置在基板上并且位于有源区域内。 虚拟栅极结构设置在基板上并且位于有源区域之外。 每个虚拟栅极结构的边缘与有效区域的边界分开，距离小于135埃。 外延结构被布置在栅极结构的两侧的有源区域内和衬底的一部分中。 本发明还提供了一种制造半导体器件的方法。

公开(公告)号：US09373718B2

公开(公告)日：2016-06-21

申请号：US14548239

申请日：2014-11-19

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Jhen-Cyuan Li ,  Shui-Yen Lu ,  Man-Ling Lu ,  Yu-Cheng Tung ,  Chung-Fu Chang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted -symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.

Abstract translation: 提供一种适于在Si衬底中形成凹槽的蚀刻方法和由其制造的FinFET晶体管。 蚀刻方法包括提供硅衬底，形成在硅衬底上的至少两个栅极结构和设置在硅衬底上的至少两个栅极间隔结构; 在硅衬底上执行第一蚀刻工艺以形成第一凹槽，其具有基部和两个倾斜侧壁，分别上升到栅极结构的各个底部，并分别与基底互连; 以及在所述第一槽的底部对所述硅衬底进行第二蚀刻处理，以形成倒立符形状的第二槽，其中所述第一槽的两个倾斜侧壁分别与所述第二槽互连，并且 第一蚀刻工艺与第二蚀刻工艺基本不同。

公开(公告)号：US11372324B2

公开(公告)日：2022-06-28

申请号：US16272889

申请日：2019-02-11

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh ,  Fan Wei Lin

IPC: G03F1/36 ,  G03F1/38 ,  G03F1/84 ,  G03F7/20

Abstract: A method for correcting a mask pattern includes: providing an original mask pattern including at least one dense pattern area and at least one isolated pattern area, and the original mask pattern being divided into a first pattern and a second pattern, wherein the first pattern is formed in the isolated pattern area and extends to the dense pattern area, and the second pattern is formed in the dense pattern area; forming at least one slot on at least one section of the first pattern, and the at least one section of the first pattern is located on at least one transition area between the at least one isolated pattern area and the at least one dense pattern area; and performing an optical proximity correction operation on the first pattern formed with at least one slot and the second pattern. Using the corrected mask pattern may avoid the occurrence of necking or breaking on portion of the post-transfer pattern.