公开(公告)号：US20230058180A1

公开(公告)日：2023-02-23

申请号：US17505686

申请日：2021-10-20

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Yu-Shen Chen ,  Chung-Yu Lan

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/32 ,  H05K3/02 ,  H05K3/42

Abstract: A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

公开(公告)号：US11792939B2

公开(公告)日：2023-10-17

申请号：US17505686

申请日：2021-10-20

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Yu-Shen Chen ,  Chung-Yu Lan

IPC: H05K1/02 ,  H05K3/02 ,  H01L23/13 ,  H01L23/485 ,  H05K1/18 ,  H05K3/32 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/186 ,  H05K1/0218 ,  H05K3/02 ,  H05K3/328 ,  H05K3/421 ,  H05K3/0047 ,  H05K2201/0723 ,  H05K2201/10454 ,  H05K2201/10636 ,  H05K2203/0285 ,  H05K2203/0292 ,  H05K2203/0723

Abstract: A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

公开(公告)号：US11924961B2

公开(公告)日：2024-03-05

申请号：US17661284

申请日：2022-04-28

Applicant: Unimicron Technology Corp.

Inventor： Ai Jing Lin ,  Chung-Yu Lan ,  Jia Hao Liang

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K1/0204 ,  H05K1/115 ,  H05K3/0061 ,  H05K2201/09509 ,  H05K2201/10416

Abstract: A circuit board includes a conductive metal layer, at least one insulating layer, at least one thermally conductive insulating layer and a heat dissipation element. The conductive metal layer is mainly used to transmit electronic signals. The insulating layer is connected to the conductive metal layer. The thermally conductive insulating layer is sandwiched between the conductive metal layer and the insulating layer, and thermally contacts the conductive metal layer, and is used for thermally conducting the heat of the conductive metal layer. The heat dissipation element is in thermal contact with the thermally conductive insulating layer, and is used to conduct the heat of the thermally conductive insulating layer to the outside through a heat dissipation channel.

公开(公告)号：US11670520B2

公开(公告)日：2023-06-06

申请号：US17523093

申请日：2021-11-10

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Jia Shiang Chen ,  Chung-Yu Lan ,  Yu-Shen Chen

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H05K1/18 ,  H01L25/065

CPC classification number: H01L21/486 ,  H01L23/49805 ,  H01L23/5384 ,  H01L25/0657 ,  H05K1/182 ,  H05K1/186 ,  H01L2225/06517 ,  H01L2225/06572

Abstract: A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps. Hence, area of the daughter substrate unit is reduced; lengths of the interconnection paths are shortened, and qualities of communication and space utilization are enhanced.