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    SEMICONDUCTOR STRUCTURE WITH AN EPITAXIAL LAYER
    1.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH AN EPITAXIAL LAYER 有权

    公开(公告)号：US20210242018A1

    公开(公告)日：2021-08-05

    申请号：US17218112

    申请日：2021-03-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

    IPC: H01L21/02 ,  H01L29/20 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00

    Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

    METAL GATE STRUCTURE
    2.
    发明申请
    METAL GATE STRUCTURE 有权
    金属门结构

    公开(公告)号：US20160027892A1

    公开(公告)日：2016-01-28

    申请号：US14852624

    申请日：2015-09-13

    Applicant: United Microelectronics Corp.

    Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

    IPC: H01L29/49 ,  H01L29/423 ,  H01L27/088

    CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

    Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

    Abstract translation: 金属栅极结构至少包括衬底，电介质层，第一和第二沟槽，第一金属层和第二金属层以及两个盖层。 特别地，介电层设置在基板上，并且第一和第二沟槽设置在电介质层中。 第一沟槽的宽度小于第二沟槽的宽度。 第一和第二金属层分别设置在第一沟槽和第二沟槽中，第一金属层的高度小于或等于第二金属层的高度。 盖层分别设置在第一金属层的顶表面和第二金属层的顶表面中。

    SEMICONDUCTOR STRUCTURE INCLUDING SILICON AND OXYGEN-CONTAINING METAL LAYER AND PROCESS THEREOF
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE INCLUDING SILICON AND OXYGEN-CONTAINING METAL LAYER AND PROCESS THEREOF 有权
    包含含硅和含氧金属层的半导体结构及其工艺

    公开(公告)号：US20160020104A1

    公开(公告)日：2016-01-21

    申请号：US14334680

    申请日：2014-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Lin ,  An-Chi Liu ,  Hsiao-Pang Chou

    IPC: H01L21/28 ,  H01L29/49 ,  H01L21/306

    CPC classification number: H01L21/28088 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

    Abstract: A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H2O2 with the concentration of 0˜0.5 weight percent (wt. %) is performed to polish the metal layer until the barrier layer on the first dielectric layer is exposed. A second chemical mechanical polishing process including a slurry of H2O2 with the concentration higher than 1 weight percent (wt. %) is performed to polish the barrier layer as well as oxidize a surface of the metal layer remaining in the trench until the first dielectric layer is exposed, thereby a metal oxide layer being formed on the metal layer.

    Abstract translation: 用于抛光和氧化的金属浇口工艺包括以下步骤。 在衬底上形成具有沟槽的第一电介质层。 依次形成阻挡层和金属层以覆盖沟槽和第一介电层。 执行包括浓度为0〜0.5重量％（重量％）的H 2 O 2的浆料的第一化学机械抛光工艺，以抛光金属层直到暴露第一​​介电层上的阻挡层。 执行包括浓度高于1重量％（重量％）的H 2 O 2的浆料的第二化学机械抛光方法以抛光阻挡层以及氧化残留在沟槽中的金属层的表面，直到第一介电层 被暴露，从而在金属层上形成金属氧化物层。

    Semiconductor structure including silicon and oxygen-containing metal layer and process thereof
    8.
    发明授权
    Semiconductor structure including silicon and oxygen-containing metal layer and process thereof 有权
    包括硅和含氧金属层的半导体结构及其工艺

    公开(公告)号：US09384985B2

    公开(公告)日：2016-07-05

    申请号：US14334680

    申请日：2014-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Lin ,  An-Chi Liu ,  Hsiao-Pang Chou

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/51

    CPC classification number: H01L21/28088 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

    Abstract: A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H2O2 with the concentration of 0˜0.5 weight percent (wt. %) is performed to polish the metal layer until the barrier layer on the first dielectric layer is exposed. A second chemical mechanical polishing process including a slurry of H2O2 with the concentration higher than 1 weight percent (wt. %) is performed to polish the barrier layer as well as oxidize a surface of the metal layer remaining in the trench until the first dielectric layer is exposed, thereby a metal oxide layer being formed on the metal layer.

    Abstract translation: 用于抛光和氧化的金属浇口工艺包括以下步骤。 在衬底上形成具有沟槽的第一电介质层。 依次形成阻挡层和金属层以覆盖沟槽和第一介电层。 执行包括浓度为0〜0.5重量％（重量％）的H 2 O 2的浆料的第一化学机械抛光工艺，以抛光金属层直到暴露第一​​介电层上的阻挡层。 执行包括浓度高于1重量％（重量％）的H 2 O 2的浆料的第二化学机械抛光方法以抛光阻挡层以及氧化残留在沟槽中的金属层的表面，直到第一介电层 被暴露，从而在金属层上形成金属氧化物层。

    Semiconductor structure with an epitaxial layer
    9.
    发明授权
    Semiconductor structure with an epitaxial layer 有权

    公开(公告)号：US11450747B2

    公开(公告)日：2022-09-20

    申请号：US17218112

    申请日：2021-03-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

    IPC: H01L29/04 ,  H01L29/20 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00 ,  H01L33/00 ,  H01L33/12 ,  H01L33/16 ,  H01L29/165

    Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

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