公开(公告)号：US09418853B1

公开(公告)日：2016-08-16

申请号：US14692736

申请日：2015-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Wei Wang ,  Keng-Jen Lin ,  Yu-Tung Hsiao ,  Shu-Ming Yeh

IPC: H01L21/3205 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795

Abstract: The present invention provides a method for forming a stacked layer structure, including: first, a recess is provided, next, an oxide layer is formed in the recess, where the oxide layer has a thickness T1, a high-k layer is formed on the oxide layer, a barrier layer is formed on the high-k layer, a silicon layer is then formed on the barrier layer, afterwards, an annealing process is performed on the silicon layer, so as to form an oxygen-containing layer between the silicon layer and the barrier layer, where the oxide layer has a thickness T2 after the annealing process is performed, and satisfies the relationship: (T2−T1)/T1≦0.05, and the silicon layer and the oxygen-containing layer are removed.

Abstract translation: 本发明提供一种层叠结构体的形成方法，其特征在于，首先，设置凹部，在所述凹部形成有氧化层，其中氧化物层的厚度为T1，高k层形成在 氧化物层，在高k层上形成阻挡层，然后在阻挡层上形成硅层，然后在硅层上进行退火处理，以在其之间形成含氧层 硅层和阻挡层，其中氧化物层在退火处理之后具有厚度T2，并且满足关系：（T2-T1）/T1≤0.05，并且去除硅层和含氧层。

公开(公告)号：US11114331B2

公开(公告)日：2021-09-07

申请号：US16431684

申请日：2019-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Hung-Chun Lee ,  Shu-Ming Yeh ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.

公开(公告)号：US20160225872A1

公开(公告)日：2016-08-04

申请号：US14609446

申请日：2015-01-30

Applicant: United Microelectronics Corp.

Inventor： Shao-Wei Wang ,  Shu-Ming Yeh ,  Yu-Tung Hsiao

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic. The first gate oxide is formed by a thermal oxidation process. The second gate oxide is formed by a chemical treatment.

Abstract translation: 提供具有多层栅极氧化物的半导体结构。 该结构包括基底。 多层栅极氧化物设置在基板上，其中多层栅极氧化物包括第一栅极氧化物和第二栅极氧化物。 第一栅极氧化物接触衬底，并且第二栅极氧化物设置在第一栅极氧化物上并与其接触。 第二栅极氧化物是亲水的。 第一栅极氧化物通过热氧化工艺形成。 第二栅极氧化物通过化学处理形成。

公开(公告)号：US20200350199A1

公开(公告)日：2020-11-05

申请号：US16431684

申请日：2019-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Hung-Chun Lee ,  Shu-Ming Yeh ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.

公开(公告)号：US09793174B1

公开(公告)日：2017-10-17

申请号：US15270000

申请日：2016-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Wei Huang ,  Yu-Ren Wang ,  Keng-Jen Lin ,  Shu-Ming Yeh

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L21/76224 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A fin field effect transistor (FinFET) on a silicon-on-insulator and method of forming the same are provided in the present invention. The FinFET includes first fin structure, second fin structure and an insulating layer. The first fin structure and the second fin structure are disposed on a substrate. The insulating layer covers the first fin structure and the second fin structure and exposes a first portion of the first fin structure and a second portion of the second fin structure. The first fin structure has a first height and the second fin structure has a second height different from the first height, and a top surface of the first fin structure and a top surface of the second fin structure are at different levels.

公开(公告)号：US09406772B1

公开(公告)日：2016-08-02

申请号：US14609446

申请日：2015-01-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Wei Wang ,  Shu-Ming Yeh ,  Yu-Tung Hsiao

IPC: H01L29/76 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic. The first gate oxide is formed by a thermal oxidation process. The second gate oxide is formed by a chemical treatment.

Abstract translation: 提供具有多层栅极氧化物的半导体结构。 该结构包括基底。 多层栅极氧化物设置在基板上，其中多层栅极氧化物包括第一栅极氧化物和第二栅极氧化物。 第一栅极氧化物接触衬底，并且第二栅极氧化物设置在第一栅极氧化物上并与其接触。 第二栅极氧化物是亲水的。 第一栅极氧化物通过热氧化工艺形成。 第二栅极氧化物通过化学处理形成。