公开(公告)号：US08450169B2

公开(公告)日：2013-05-28

申请号：US12954946

申请日：2010-11-29

申请人： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

发明人： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

IPC分类号： H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

摘要翻译： 可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。 此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。 在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。 图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的阻挡金属层上。 导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

公开(公告)号：US20120132998A1

公开(公告)日：2012-05-31

申请号：US12954946

申请日：2010-11-29

申请人： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

发明人： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L27/092 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

摘要翻译： 可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。 此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。 在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。 图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。 导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

公开(公告)号：US08759172B2

公开(公告)日：2014-06-24

申请号：US13449433

申请日：2012-04-18

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

公开(公告)号：US20130277764A1

公开(公告)日：2013-10-24

申请号：US13449433

申请日：2012-04-18

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

公开(公告)号：US20100187610A1

公开(公告)日：2010-07-29

申请号：US12359520

申请日：2009-01-26

申请人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

发明人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.

摘要翻译： 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

公开(公告)号：US07838908B2

公开(公告)日：2010-11-23

申请号：US12359520

申请日：2009-01-26

申请人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

发明人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

IPC分类号： H01L27/10

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.

摘要翻译： 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

公开(公告)号：US07691701B1

公开(公告)日：2010-04-06

申请号：US12348332

申请日：2009-01-05

申请人： Michael P. Belyansky ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Ravikumar Ramachandran ,  James Kenyon Schaeffer ,  Richard Wise ,  Keith Kwong Hon Wong ,  Hongwen Yan

发明人： Michael P. Belyansky ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Ravikumar Ramachandran ,  James Kenyon Schaeffer ,  Richard Wise ,  Keith Kwong Hon Wong ,  Hongwen Yan

IPC分类号： H01L21/00

CPC分类号： H01L21/823842 ,  H01L21/823857

摘要： Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and second types of field-effect-transistors; forming a capping layer of a second TiN layer on top of the metal-containing layer; patterning the second TiN layer and the metal-containing layer to cover only a first portion of the first TiN layer, the first portion of the first TiN layer covering an area designated for the first type of field-effect-transistors; etching away a second portion of the first TiN layer exposed by the patterning while protecting the first portion of the first TiN layer, from the etching, through covering with at least a portion of thickness of the patterned metal-containing layer; and forming a third TiN layer covering an areas of the semiconductor substrate designated for the second type of field-effect-transistors.

摘要翻译： 本发明的实施例提供了一种形成场效应晶体管的栅叠层的方法。 该方法包括直接在第一氮化钛（TiN）层上形成含金属层，第一TiN层覆盖用于第一和第二类场效应晶体管的半导体衬底的区域; 在所述含金属层的顶部上形成第二TiN层的覆盖层; 图案化第二TiN层和含金属层以仅覆盖第一TiN层的第一部分，第一TiN层的第一部分覆盖指定用于第一类型的场效应晶体管的区域; 蚀刻通过图案化暴露的第一TiN层的第二部分，同时通过覆盖图案化的含金属层的厚度的至少一部分来保护第一TiN层的第一部分免受蚀刻; 以及形成覆盖指定用于第二类场效应晶体管的半导体衬底的区域的第三TiN层。

公开(公告)号：US08941177B2

公开(公告)日：2015-01-27

申请号：US13534012

申请日：2012-06-27

申请人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

发明人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC分类号： H01L29/36 ,  H01L29/66

CPC分类号： H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

公开(公告)号：US20120139053A1

公开(公告)日：2012-06-07

申请号：US12960586

申请日：2010-12-06

申请人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

发明人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7848

摘要： A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

摘要翻译： 同时制造n型和p型场效应晶体管的方法可以包括在覆盖第一有源半导体区域的电介质区域中的第一开口中形成具有与栅极电介质层相邻的第一栅极金属层的第一替代栅极。 包括第二栅极金属层的第二替代栅极可以在覆盖在第二有源半导体区域上的电介质区域中的第二开口中邻近栅极电介质层形成。 第一和第二栅极金属层的至少一部分可以沿其厚度的方向堆叠并且通过至少阻挡金属层彼此分离。 由该方法产生的NFET可以包括第一有源半导体区域，其中的源极/漏极区域和第一替换栅极，并且由该方法产生的PFET可以包括第二有源半导体区域，其中的源/漏区域和第二替换 门。

公开(公告)号：US08575709B2

公开(公告)日：2013-11-05

申请号：US13556795

申请日：2012-07-24

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/2822 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66575

摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

摘要翻译： 用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。 在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。 在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。