公开(公告)号：US10468830B2

公开(公告)日：2019-11-05

申请号：US15092616

申请日：2016-04-07

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H01R13/658 ,  H01R13/6591 ,  H01R13/6585 ,  H01R13/66 ,  H05K1/02 ,  H05K1/11

Abstract: A paddle card includes a circuit board, a pad group and ground planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads and the pair of lower differential pads are corresponding to each other respectively and configured up and down. The ground planes are spaced at intervals between the upper surface and the lower surface. The ground plane below the pair of upper differential pads has an opening corresponding thereto. A portion of the at least one ground plane between the pair of upper differential pads and the pair of lower differential pads is solid as a shield.

公开(公告)号：US10218127B2

公开(公告)日：2019-02-26

申请号：US15640599

申请日：2017-07-03

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H01R13/658 ,  H01R13/6585 ,  H01R13/6588 ,  H01R12/53 ,  H01R12/72 ,  H01R24/28 ,  H01R24/60 ,  H05K3/40 ,  H01R107/00

Abstract: A paddle card includes a circuit board, a pad group and first to fourth shielding planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads is respectively configured corresponding to the pair of lower differential pads in an up and down manner. The first to fourth shielding planes are stacked at intervals between the upper and lower surfaces in sequence. An orthogonal projection of a second opening of the second shielding plane on a geometric plane that a pair of third openings of the third shielding plane is located in is separate from the pair of third openings.

公开(公告)号：US10103217B2

公开(公告)日：2018-10-16

申请号：US15971218

申请日：2018-05-04

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/522 ,  H01L29/06 ,  H01L23/528

Abstract: A semiconductor device includes an insulating layer disposed over a substrate, wherein the insulating layer has a center region. A first winding portion and a second winding portion are electrically connected to the first winding portion, disposed in a first level of the insulating layer and surrounding the center region, wherein each of the first winding portion and the second winding portion comprises a plurality of conductive lines arranged from the inside to the outside. A first extending conductive line and a second extending conductive line partially surround the first extending conductive line, and are disposed in the first level of the insulating layer, wherein the first winding portion and the second winding portion surround the first extending conductive line and the second extending conductive line. A third extending conductive line is disposed in a second level of the insulating layer and surrounding the center region.

公开(公告)号：US20180138639A1

公开(公告)日：2018-05-17

申请号：US15640599

申请日：2017-07-03

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H01R13/6585 ,  H01R24/28 ,  H01R12/53 ,  H01R12/72

CPC classification number: H01R13/6585 ,  H01R12/53 ,  H01R12/722 ,  H01R12/727 ,  H01R13/6588 ,  H01R24/28 ,  H01R24/60 ,  H01R2107/00 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/0298 ,  H05K3/40 ,  H05K2201/0723

Abstract: A paddle card includes a circuit board, a pad group and first to fourth shielding planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads is respectively configured corresponding to the pair of lower differential pads in an up and down manner. The first to fourth shielding planes are stacked at intervals between the upper and lower surfaces in sequence. An orthogonal projection of a second opening of the second shielding plane on a geometric plane that a pair of third openings of the third shielding plane is located in is separate from the pair of third openings.

公开(公告)号：US09583555B2

公开(公告)日：2017-02-28

申请号：US14813510

申请日：2015-07-30

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate having a center region. The semiconductor device includes a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center region A second conductive line and a third conductive line are arranged from the inside to the outside. In addition, each of the first, second and third conductive lines has a first end and a second end. The semiconductor device also includes a coupling portion disposed in the first and second insulating layers between the first and second winding portions, and having a first pair of connection layers cross-connecting the second ends of the first and second conductive lines, and a second pair of connection layers cross-connecting the first ends of the second and third conductive lines.

Abstract translation: 一种半导体器件，包括顺序地设置在具有中心区域的衬底上的第一绝缘层和第二绝缘层。 半导体器件包括设置在第二绝缘层中并围绕中心区域的第一绕组部分和第二绕组部分，从内向外布置第二导线和第三导线。 此外，第一，第二和第三导线中的每一个具有第一端和第二端。 该半导体器件还包括一个耦合部分，设置在第一和第二绕组部分之间的第一和第二绝缘层中，并具有交叉连接第一和第二导线的第二端的第一对连接层，以及第二对 的连接层交叉连接第二和第三导线的第一端。

公开(公告)号：US09444165B2

公开(公告)日：2016-09-13

申请号：US14551094

申请日：2014-11-24

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H01R12/00 ,  H01R12/77 ,  H05K1/02 ,  H05K1/14 ,  H01R13/6473 ,  H01R13/6471 ,  H05K1/11

CPC classification number: H01R12/771 ,  H01R13/6471 ,  H01R13/6473 ,  H05K1/025 ,  H05K1/117 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/09781 ,  H05K2201/10189

Abstract: A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.

Abstract translation: 提供一种适于FPC连接器的插脚布置。 引脚布置包括引脚通道。 引脚通道包括一对接地引脚，一对差分引脚和至少一个未连接（NC）引脚。 差分引脚位于一对接地引脚之间。 所述至少一个NC销位于所述一对差动销之间，或位于所述一对接地引脚中的一个与所述一对接地引脚中的一个与其相邻的所述一对差动引脚之一中。 通过在所述一对差动引脚之间和/或差分引脚和与其相邻的接地引脚之间增加至少一个NC引脚，所述一对差动引脚和/或差分引脚与接地引脚之间的距离 因此增加了一对差分引脚的差分特性阻抗，以减少阻抗失配的影响。

公开(公告)号：US20160021735A1

公开(公告)日：2016-01-21

申请号：US14534170

申请日：2014-11-06

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K1/182 ,  H05K2201/042 ,  H05K2201/10189

Abstract: A through-hole layout structure is suitable for a circuit board. The through-hole layout structure includes a pair of first differential through-holes, a pair of second differential through-holes, a first ground through-hole, a second ground through-hole, and a third ground through-hole, which are all arranged on a first line.The first ground through-hole is located between the pair of first differential through-holes and the pair of second differential through-holes. The pair of first differential through-holes is located between the first ground through-hole and the second ground through-hole. The pair of second differential through-holes is located between the first ground through-hole and the third ground through-hole.

Abstract translation: 通孔布局结构适用于电路板。 通孔布局结构包括一对第一差分通孔，一对第二差分通孔，第一接地通孔，第二接地通孔和第三接地通孔，这些都是 安排在第一行。 第一接地通孔位于一对第一差分通孔和一对第二差动通孔之间。 一对第一差分通孔位于第一接地通孔和第二接地通孔之间。 一对第二差分通孔位于第一接地通孔和第三接地通孔之间。

公开(公告)号：US09142541B2

公开(公告)日：2015-09-22

申请号：US14076419

申请日：2013-11-11

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L27/02 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines.

Abstract translation: 公开了一种包括顺序地设置在基板上的第一绝缘层和第二绝缘层的半导体器件。 第一导电线和第二导线设置在第一绝缘层中，并且第一和第二导线中的每一个具有第一端和第二端，其中第一和第二导线的第二端耦合到每个 其他。 第一绕组部分和第二绕组部分设置在第二绝缘层中，并且第一和第二绕组部分中的每一个包括从内向外布置的第三导线和第四导线。 第三和第四导线中的每一个具有第一端和第二端，其中第一和第二导线与第三导线的至少一部分重叠。

公开(公告)号：US09991327B2

公开(公告)日：2018-06-05

申请号：US15440082

申请日：2017-02-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/528 ,  H01L29/06 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L29/0619

Abstract: A semiconductor device includes first and second winding portions disposed in a first level of an insulating layer and surrounding a center region thereof. Each of the winding portions includes conductive lines arranged from the inside to the outside. First and second extending conductive lines are disposed in the first level of the insulating layer. A third extending conductive line is disposed in a second level of the insulating layer. The first extending conductive line is coupled between the innermost conductive line of the second winding and the third extending conductive line. The second extending conductive line is coupled between the innermost conductive line of the first winding portion and the third extending conductive line. The first extending conductive line and the third extending conductive line coupled thereto are arranged in a helix or a spiral spatial configuration.

公开(公告)号：US20170062991A1

公开(公告)日：2017-03-02

申请号：US15092616

申请日：2016-04-07

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H01R13/6591 ,  H01R24/28

CPC classification number: H01R13/6591 ,  H01R13/6585 ,  H01R13/6658 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/117 ,  H05K2201/09309

Abstract: A paddle card includes a circuit board, a pad group and ground planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads and the pair of lower differential pads are corresponding to each other respectively and configured up and down. The ground planes are spaced at intervals between the upper surface and the lower surface. The ground plane below the pair of upper differential pads has an opening corresponding thereto. A portion of the at least one ground plane between the pair of upper differential pads and the pair of lower differential pads is solid as a shield.

Abstract translation: 桨卡包括电路板，焊盘组和接地层。 电路板具有彼此相对的上表面和下表面。 焊盘组适于连接电缆或插头的端子的导线，并且在上表面上包括一对上差分焊盘和下表面上的一对下差分焊盘。 一对上差速器垫和一对下差速器垫分别彼此对应并配置为上下。 接地平面在上表面和下表面之间间隔开。 一对上差速器垫下方的接地平面具有对应的开口。 一对上差速器垫和一对下差速器垫之间的至少一个接地平面的一部分是实心的屏蔽。