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    Two Partition Accelerator and Application of Tiered Flash to Cache Hierarchy in Partition Acceleration
    6.
    发明申请
    Two Partition Accelerator and Application of Tiered Flash to Cache Hierarchy in Partition Acceleration 失效
    分区加速器的两个分区加速器和应用分区加速中的缓存层次结构

    公开(公告)号：US20110022803A1

    公开(公告)日：2011-01-27

    申请号：US12508621

    申请日：2009-07-24

    申请人： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

    发明人： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0811 ,  G06F2212/1024 ,  G06F2212/1032

    摘要： An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.

    摘要翻译： 提供了一种用于从包括在处理节点中的一组处理核心识别禁用的处理核心和活动处理核心的方法。 每个处理核心被分配一个高速缓冲存储器。 该方法扩展了分配给活动处理核心的高速缓存存储器的存储器映射，以包括分配给禁用处理核心的高速缓存存储器。 由第一进程使用的第一数据量由活动处理核存储到分配给活动处理核的高速缓冲存储器。 第二数据量由活动处理核心使用扩展存储器映射存储到分配给非活动处理核心的缓存存储器。

    Flexible use of extended cache using a partition cache footprint
    7.
    发明申请
    Flexible use of extended cache using a partition cache footprint 失效
    灵活使用扩展缓存使用分区缓存占用空间

    公开(公告)号：US20120042131A1

    公开(公告)日：2012-02-16

    申请号：US12856682

    申请日：2010-08-15

    申请人： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

    发明人： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0811 ,  G06F12/0284 ,  G06F2212/502 ,  G06F2212/604

    摘要： An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.

    摘要翻译： 提供了一种方法来识别对应于在计算机系统上运行的不同分区的高速缓存扩展大小。 该方法利用来自系统存储器区域的第一存储器分配来扩展与包括在处理器的硅衬底中的第一处理核心相关联的第一硬件高速缓存，系统存储器区域在硅衬底外部，并且第一存储器分配对应于 多个缓存扩展大小中的一个对应于在计算机系统上运行的分区之一。 该方法进一步扩展与第二处理核心相关联的第二硬件高速缓存，该第二处理核心还包括在处理器的硅衬底中，具有来自系统存储区域的第二存储器分配，其中第二存储器分配对应于对应于不同分区的另一个高速缓存扩展大小 正在由第二处理核心执行。

    Bus access moderation system
    8.
    发明授权
    Bus access moderation system 失效
    总线访问管理系统

    公开(公告)号：US07962677B2

    公开(公告)日：2011-06-14

    申请号：US12173211

    申请日：2008-07-15

    申请人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

    发明人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

    IPC分类号： G06F13/00

    CPC分类号： G06F9/485 ,  G06F9/4881

    摘要： A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable. In one example, the number of simultaneous multithreading (SMT) threads per core will be reduced using a system call. This effectively throttles back the amount of logical threads per core and effectively alleviates the bus request saturation.

    摘要翻译： 提供了一种方法，编程介质和系统，其中系统总线流量由实时数据调节。 操作系统（OS）能够从固件（FW）获取信息，以确定是否已达到资源阈值。 这通过在总线请求重试速率达到预定数量时产生中断来标记OS来实现。 系统固件在此机制中起着不可或缺的作用，应该被解释为一个通用术语，也可以包括管理程序技术。 系统固件将通过例如固件产生的中断来向总线请求重试率报告给操作系统。 操作系统可能与内核守护程序/服务类似，以拦截中断通知。 在最简单的情况下，守护程序/服务将根据固件的反馈来确定阈值是否得到满足。 如果是这样，它将生成一个系统调用，以便通过操作系统可调整来调节流量。 在一个示例中，使用系统调用将减少每个内核的同时多线程（SMT）线程数。 这有效地节省了每个内核的逻辑线程数量，并有效地缓解了总线请求饱和度。

    BUS ACCESS MODERATION SYSTEM
    9.
    发明申请
    BUS ACCESS MODERATION SYSTEM 失效
    总线访问调制系统

    公开(公告)号：US20100017551A1

    公开(公告)日：2010-01-21

    申请号：US12173211

    申请日：2008-07-15

    申请人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

    发明人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

    IPC分类号： G06F13/14

    CPC分类号： G06F9/485 ,  G06F9/4881

    摘要： A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable. In one example, the number of simultaneous multithreading (SMT) threads per core will be reduced using a system call. This effectively throttles back the amount of logical threads per core and effectively alleviates the bus request saturation.

    摘要翻译： 提供了一种方法，编程介质和系统，其中系统总线流量由实时数据调节。 操作系统（OS）能够从固件（FW）获取信息，以确定是否已达到资源阈值。 这通过在总线请求重试速率达到预定数量时产生中断来标记OS来实现。 系统固件在此机制中起着不可或缺的作用，应该被解释为一个通用术语，也可以包括管理程序技术。 系统固件将通过例如固件产生的中断来向总线请求重试率报告给操作系统。 操作系统可能与内核守护程序/服务类似，以拦截中断通知。 在最简单的情况下，守护程序/服务将根据固件的反馈来确定阈值是否得到满足。 如果是这样，它将生成一个系统调用，以便通过操作系统可调整来调节流量。 在一个示例中，使用系统调用将减少每个内核的同时多线程（SMT）线程数。 这有效地节省了每个内核的逻辑线程数量，并有效地缓解了总线请求饱和度。

    Standalone software performance optimizer system for hybrid systems
    10.
    发明授权
    Standalone software performance optimizer system for hybrid systems 有权
    混合系统的独立软件性能优化系统

    公开(公告)号：US08745622B2

    公开(公告)日：2014-06-03

    申请号：US12427746

    申请日：2009-04-22

    申请人： Greg R. Mewhinney ,  Diane Garza Flemming ,  David B. Whitworth ,  William A. Maron ,  Mysore Sathyanarayana Srinivas

    发明人： Greg R. Mewhinney ,  Diane Garza Flemming ,  David B. Whitworth ,  William A. Maron ,  Mysore Sathyanarayana Srinivas

    IPC分类号： G06F9/50 ,  G06F9/48

    CPC分类号： G06F9/5033 ,  G06F9/4843 ,  G06F9/50 ,  G06F9/5044

    摘要： Standalone software performance optimizer systems for hybrid systems include a hybrid system having a plurality of processors, memory operably connected to the processors, an operating system including a dispatcher loaded into the memory, a multithreaded application read into the memory, and a static performance analysis program loaded into the memory; wherein the static performance analysis program instructs at least one processor to perform static performance analysis on each of the threads, the static performance analysis program instructs at least one processor to assign each thread to a CPU class based on the static performance analysis, and the static performance analysis program instructs at least one processor to store each thread's CPU class. An embodiment of the invention may also include the dispatcher optimally mapping threads to processors using thread CPU classes and remapping threads to processors when a runtime performance analysis classifies a thread differently from the static performance analysis.

    摘要翻译： 用于混合系统的独立软件性能优化器系统包括具有多个处理器的混合系统，可操作地连接到处理器的存储器，包括加载到存储器中的调度器，读入存储器的多线程应用的操作系统和静态性能分析程序 加载到内存中; 其中所述静态性能分析程序指示至少一个处理器对每个所述线程执行静态性能分析，所述静态性能分析程序指示至少一个处理器基于所述静态性能分析将每个线程分配给CPU类，并且所述静态 性能分析程序指示至少一个处理器存储每个线程的CPU类。 本发明的实施例还可以包括调度器，当运行时性能分析将线程与静态性能分析不同的方式进行分类时，线程CPU类将线程最优地映射到处理器并将线程重新映射到处理器。