公开(公告)号：US08972706B2

公开(公告)日：2015-03-03

申请号：US13116515

申请日：2011-05-26

申请人： Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

发明人： Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/38 ,  G06F9/3806 ,  G06F9/3848

摘要： A data processing system and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

摘要翻译： 用于处理指令的数据处理系统和计算机程序产品。 所述指令由处理器单元处理，同时使用多个表中的第一表来预测在处理条件指令之后所述处理器单元所需的一组指令。 形成识别，即当使用第一表时正确预测指令集的成功率小于阈值数。 搜索由处理器单元处理的指令的序列，以搜索与用于识别何时使用多个表的一组标记中的标记相匹配的指令。 形成与标记相符的指令的标识。 识别由标记引用的多个表中的第二表。 第二个表用于代替第一个表。

公开(公告)号：US20130111135A1

公开(公告)日：2013-05-02

申请号：US13286507

申请日：2011-11-01

申请人： Robert H. Bell, JR. ,  Wen-Tzer T. Chen ,  Diane G. Flemming ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

发明人： Robert H. Bell, JR. ,  Wen-Tzer T. Chen ,  Diane G. Flemming ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

IPC分类号： G06F12/08

CPC分类号： G06F12/08 ,  G06F12/0811 ,  G06F12/0897

摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.

摘要翻译： 根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。 该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小 对应于较低级别缓存的高速缓存行大小。 该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

公开(公告)号：US08407499B2

公开(公告)日：2013-03-26

申请号：US12763431

申请日：2010-04-20

申请人： Vaijayanthimala K Anand ,  Diane Garza Flemming ,  William A Maron ,  Mysore Srinivas

发明人： Vaijayanthimala K Anand ,  Diane Garza Flemming ,  William A Maron ,  Mysore Srinivas

IPC分类号： G06F1/32 ,  G06F1/24 ,  G06F9/00

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/22 ,  Y02D10/36

摘要： Handling requests for power reduction by first enabling a request for an amount of power change, e.g. reduction by any partition. In response to the request for power reduction, an equal proportion of the whole amount of power reduction is distributed between each of a set of cores providing the entitlements to the partitions, and the entitlement of the requesting partition is reduced by an amount corresponding to the whole amount of the power change.

摘要翻译： 通过首先启用功率变化量的请求来处理功率降低的请求，例如， 减少任何分区。 响应于减少功率的请求，在提供分配权利的一组核心的每一个之间分配全部功率减少的相等比例，并且请求分区的授权减少对应于 整个功率的变化量。

公开(公告)号：US20120042131A1

公开(公告)日：2012-02-16

申请号：US12856682

申请日：2010-08-15

申请人： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

发明人： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0284 ,  G06F2212/502 ,  G06F2212/604

摘要： An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.

摘要翻译： 提供了一种方法来识别对应于在计算机系统上运行的不同分区的高速缓存扩展大小。 该方法利用来自系统存储器区域的第一存储器分配来扩展与包括在处理器的硅衬底中的第一处理核心相关联的第一硬件高速缓存，系统存储器区域在硅衬底外部，并且第一存储器分配对应于 多个缓存扩展大小中的一个对应于在计算机系统上运行的分区之一。 该方法进一步扩展与第二处理核心相关联的第二硬件高速缓存，该第二处理核心还包括在处理器的硅衬底中，具有来自系统存储区域的第二存储器分配，其中第二存储器分配对应于对应于不同分区的另一个高速缓存扩展大小 正在由第二处理核心执行。

公开(公告)号：US07962677B2

公开(公告)日：2011-06-14

申请号：US12173211

申请日：2008-07-15

申请人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

发明人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

IPC分类号： G06F13/00

CPC分类号： G06F9/485 ,  G06F9/4881

摘要： A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable. In one example, the number of simultaneous multithreading (SMT) threads per core will be reduced using a system call. This effectively throttles back the amount of logical threads per core and effectively alleviates the bus request saturation.

摘要翻译： 提供了一种方法，编程介质和系统，其中系统总线流量由实时数据调节。 操作系统（OS）能够从固件（FW）获取信息，以确定是否已达到资源阈值。 这通过在总线请求重试速率达到预定数量时产生中断来标记OS来实现。 系统固件在此机制中起着不可或缺的作用，应该被解释为一个通用术语，也可以包括管理程序技术。 系统固件将通过例如固件产生的中断来向总线请求重试率报告给操作系统。 操作系统可能与内核守护程序/服务类似，以拦截中断通知。 在最简单的情况下，守护程序/服务将根据固件的反馈来确定阈值是否得到满足。 如果是这样，它将生成一个系统调用，以便通过操作系统可调整来调节流量。 在一个示例中，使用系统调用将减少每个内核的同时多线程（SMT）线程数。 这有效地节省了每个内核的逻辑线程数量，并有效地缓解了总线请求饱和度。

公开(公告)号：US20100017551A1

公开(公告)日：2010-01-21

申请号：US12173211

申请日：2008-07-15

申请人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

发明人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

IPC分类号： G06F13/14

CPC分类号： G06F9/485 ,  G06F9/4881

摘要： A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable. In one example, the number of simultaneous multithreading (SMT) threads per core will be reduced using a system call. This effectively throttles back the amount of logical threads per core and effectively alleviates the bus request saturation.

摘要翻译： 提供了一种方法，编程介质和系统，其中系统总线流量由实时数据调节。 操作系统（OS）能够从固件（FW）获取信息，以确定是否已达到资源阈值。 这通过在总线请求重试速率达到预定数量时产生中断来标记OS来实现。 系统固件在此机制中起着不可或缺的作用，应该被解释为一个通用术语，也可以包括管理程序技术。 系统固件将通过例如固件产生的中断来向总线请求重试率报告给操作系统。 操作系统可能与内核守护程序/服务类似，以拦截中断通知。 在最简单的情况下，守护程序/服务将根据固件的反馈来确定阈值是否得到满足。 如果是这样，它将生成一个系统调用，以便通过操作系统可调整来调节流量。 在一个示例中，使用系统调用将减少每个内核的同时多线程（SMT）线程数。 这有效地节省了每个内核的逻辑线程数量，并有效地缓解了总线请求饱和度。

公开(公告)号：US20080256302A1

公开(公告)日：2008-10-16

申请号：US11733352

申请日：2007-04-10

申请人： William A. Maron ,  Greg R. Mewhinney ,  Mysore S. Srinivas ,  David B. Whitworth

发明人： William A. Maron ,  Greg R. Mewhinney ,  Mysore S. Srinivas ,  David B. Whitworth

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method, computer program product, and system are provided for prefetching data into a cache memory. As a program is executed an object identifier is obtained of a first object of the program. A lookup operation is performed on a data structure to determine if the object identifier is present in the data structure. Responsive to the object identifier being present in the data structure, a referenced object identifier is retrieved that is referenced by the object identifier. Then, the data associated with the referenced object identifier is prefetched from main memory into the cache memory.

摘要翻译： 提供了一种用于将数据预取到高速缓冲存储器中的方法，计算机程序产品和系统。 当执行程序时，获得程序的第一对象的对象标识符。 对数据结构执行查找操作以确定对象标识符是否存在于数据结构中。 响应于数据结构中存在的对象标识符，检索由对象标识符引用的引用对象标识符。 然后，与被引用的对象标识符相关联的数据从主存储器预取到高速缓冲存储器中。

公开(公告)号：US08695011B2

公开(公告)日：2014-04-08

申请号：US13458769

申请日：2012-04-27

申请人： Diane G. Flemming ,  William A. Maron ,  Ram Raghavan ,  Satya Prakash Sharma ,  Mysore S. Srinivas

发明人： Diane G. Flemming ,  William A. Maron ,  Ram Raghavan ,  Satya Prakash Sharma ,  Mysore S. Srinivas

IPC分类号： G06F9/46 ,  G06F1/00 ,  G06F13/00

CPC分类号： G06F9/5077

摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.

公开(公告)号：US08539281B2

公开(公告)日：2013-09-17

申请号：US13451266

申请日：2012-04-19

申请人： Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

发明人： Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

IPC分类号： G06F11/00

CPC分类号： G06F9/528 ,  G06F9/467

摘要： According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location.

摘要翻译： 根据本公开的一个方面，公开了一种用于在事务存储器环境中管理回滚的方法和技术。 该方法包括：响应于由支持事务性存储器处理的处理器检测开始事务指令，检测不需要回滚的第一存储器位置的访问，并指示第一存储器位置不需要回滚，同时检测到对 第二个内存位置，并指示需要回滚。 该方法还包括：响应于在开始事务指令之后检测到结束事务指令和需要回滚的冲突，在第二存储器位置上执行回滚的同时省略第一存储器位置的回滚。

公开(公告)号：US08392659B2

公开(公告)日：2013-03-05

申请号：US12612767

申请日：2009-11-05

申请人： Vaijayanthimala K. Anand ,  Diane Garza Flemming ,  William A. Maron ,  Mysore Sathyanarayana Srinivas

发明人： Vaijayanthimala K. Anand ,  Diane Garza Flemming ,  William A. Maron ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F2212/601

摘要： A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.

摘要翻译： 提供了一种编程介质和系统，用于通过使用同一芯片上的禁用或非使能内核的高速缓存来实现内核的高速缓存容量的增加。 对芯片上的禁用或非启用内核的缓存进行访问，以存储已启用的那些芯片内核的高速缓存线，从而扩展启用核心的高速缓存容量。