Anti-reflective coatings for use at 248 nm and 193 nm
    2.
    发明授权
    Anti-reflective coatings for use at 248 nm and 193 nm 有权
    抗反射涂层用于248 nm和193 nm

    公开(公告)号:US06686272B1

    公开(公告)日:2004-02-03

    申请号:US10020084

    申请日:2001-12-13

    IPC分类号: H01L214763

    摘要: The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.

    摘要翻译: 本发明涉及碳化硅抗反射涂层(ARC)和碳氧化硅ARC。 另一个实施方案涉及用氧等离子体处理的碳氧化硅ARC。 本发明包括在半导体衬底表面上形成碳化硅层和碳氧化硅层作为ARC的方法实施例。 特别地,所述方法包括将甲基硅烷材料引入处理室中,其中它们被等离子体点燃并作为碳化硅沉积在基板表面上。 另一种方法包括将具有惰性载气的甲基硅烷前体材料用氧气引入到处理室中。 将这些材料点燃到等离子体中,并将​​碳氧化硅材料沉积到基底上。 通过调节氧气流速,可以调节碳硅氧烷层的光学性能。 在另一个实施方案中,可以用氧等离子体处理碳氧化硅层。

    Forming copper interconnects with Sn coatings
    3.
    发明授权
    Forming copper interconnects with Sn coatings 有权
    与Sn涂层形成铜互连

    公开(公告)号:US07675177B1

    公开(公告)日:2010-03-09

    申请号:US11074456

    申请日:2005-03-07

    IPC分类号: H01L23/48 H01L23/52 H01L29/40

    摘要: A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.

    摘要翻译: 通过在电介质层中形成沟槽,在镶嵌结构中形成具有Sn涂层的铜互连。 沟槽通过同时与金属掺杂剂电镀铜形成掺杂的铜层而形成。 掺杂铜层的顶层被还原成与第一介电层的表面形成平坦化的表面水平。 将掺杂的铜退火以驱动金属掺杂剂,以在掺杂铜层的平坦化顶表面上形成金属掺杂物覆盖涂层。

    Forming copper interconnects with Sn coatings
    4.
    发明授权
    Forming copper interconnects with Sn coatings 有权
    与Sn涂层形成铜互连

    公开(公告)号:US06884720B1

    公开(公告)日:2005-04-26

    申请号:US10648602

    申请日:2003-08-25

    摘要: A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.

    摘要翻译: 通过在电介质层中形成沟槽,在镶嵌结构中形成具有Sn涂层的铜互连。 沟槽通过同时与金属掺杂剂电镀铜形成掺杂的铜层而形成。 掺杂铜层的顶层被还原成与第一介电层的表面形成平坦化的表面水平。 将掺杂的铜退火以驱动金属掺杂剂,以在掺杂铜层的平坦化顶表面上形成金属掺杂物覆盖涂层。

    Method and structure for creating ultra low resistance damascene copper wiring
    5.
    发明授权
    Method and structure for creating ultra low resistance damascene copper wiring 有权
    制造超低电阻大马士革铜线的方法和结构

    公开(公告)号:US06987059B1

    公开(公告)日:2006-01-17

    申请号:US10641768

    申请日:2003-08-14

    IPC分类号: H01L21/4763

    摘要: A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

    摘要翻译: 通过在通孔和沟槽结构的侧壁上形成诸如SiC或SiOC的薄介电膜来形成低电阻铜镶嵌互连结构,起到铜扩散阻挡层的作用。 通过各向异性蚀刻去除在沟槽结构的底部形成的电介质铜扩散屏障,以露出图案化的金属区域。 因此,残余电介质在结构的侧壁上形成电介质扩散阻挡膜,并与随后在沟槽中形成的金属扩散阻挡层耦合,形成铜扩散阻挡层,以保护大块电介质免受铜泄漏。

    Dual damascene interconnect structure with improved electro migration lifetimes
    6.
    发明授权
    Dual damascene interconnect structure with improved electro migration lifetimes 有权
    双镶嵌互连结构,具有改善的电迁移寿命

    公开(公告)号:US07312532B2

    公开(公告)日:2007-12-25

    申请号:US11090107

    申请日:2005-03-24

    IPC分类号: H01L23/52 H01L23/48

    摘要: A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.

    摘要翻译: 通过图案化第一电介质以形成金属线来形成双镶嵌互连结构。 第二电介质设置在第一电介质上并被图案化以形成通孔。 第一金属线以相对于通孔接合的结构进行图案化,使得当将进入第二电介质的通孔蚀刻延伸到第一电介质中时形成空腔。 在形成通孔的情况下,以一体的方式填充导电金属以形成通孔突起,以改善通孔和金属线之间的电接触。

    Dual damascene interconnect structure with improved electro migration lifetimes
    7.
    发明授权
    Dual damascene interconnect structure with improved electro migration lifetimes 失效
    双镶嵌互连结构,具有改善的电迁移寿命

    公开(公告)号:US07033929B1

    公开(公告)日:2006-04-25

    申请号:US10328333

    申请日:2002-12-23

    IPC分类号: H01L21/4763

    摘要: A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.

    摘要翻译: 通过图案化第一电介质以形成金属线来形成双镶嵌互连结构。 第二电介质设置在第一电介质上并被图案化以形成通孔。 第一金属线以相对于通孔接合的结构进行图案化,使得当将进入第二电介质的通孔蚀刻延伸到第一电介质中时形成空腔。 在形成通孔的情况下,以一体的方式填充导电金属以形成通孔突起,以改善通孔和金属线之间的电接触。

    Method and structure for creating ultra low resistance damascene copper wiring
    8.
    发明授权
    Method and structure for creating ultra low resistance damascene copper wiring 有权
    制造超低电阻大马士革铜线的方法和结构

    公开(公告)号:US07196420B1

    公开(公告)日:2007-03-27

    申请号:US11259965

    申请日:2005-10-26

    IPC分类号: H01L23/48

    摘要: A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

    摘要翻译: 通过在通孔和沟槽结构的侧壁上形成诸如SiC或SiOC的薄介电膜来形成低电阻铜镶嵌互连结构,起到铜扩散阻挡层的作用。 通过各向异性蚀刻去除在沟槽结构的底部形成的电介质铜扩散屏障,以露出图案化的金属区域。 因此,残余电介质在结构的侧壁上形成电介质扩散阻挡膜,并与随后在沟槽中形成的金属扩散阻挡层耦合,形成铜扩散阻挡层,以保护大块电介质免受铜泄漏。

    Layout design and process to form nanotube cell for nanotube memory applications
    9.
    发明授权
    Layout design and process to form nanotube cell for nanotube memory applications 失效
    纳米管存储器应用的纳米管细胞的布局设计和工艺

    公开(公告)号:US06969651B1

    公开(公告)日:2005-11-29

    申请号:US10810760

    申请日:2004-03-26

    摘要: Nanotube memory cells are formed on a semiconductor substrate. Lower and upper memory cell chambers are formed by forming a first trench overlying the first and second contacts in a nitride layer, forming a second trench overlying the first and second contacts in a dielectric layer, depositing a nitride layer on the combined lower and upper chambers, and patterning the nitride layer to form an access hole to the nanotube layer and a second access hole to the second contact. A conductive layer is then deposited and patterned to form a top electrode contact and a nanotube layer contact. The conductive material closes the aperture created by the access hole.

    摘要翻译: 纳米管存储单元形成在半导体衬底上。 下部和上部存储单元室通过在氮化物层中形成覆盖第一和第二触点的第一沟槽形成,形成覆盖介电层中的第一和第二触点的第二沟槽,在组合的下部和上部腔室上沉积氮化物层 并且图案化氮化物层以形成到纳米管层的访问孔和到第二接触的第二访问孔。 然后沉积导电层并图案化以形成顶部电极接触和纳米管层接触。 导电材料封闭由进入孔产生的孔。

    Dual damascene interconnect structure with improved electro migration lifetimes
    10.
    发明申请
    Dual damascene interconnect structure with improved electro migration lifetimes 有权
    双镶嵌互连结构,具有改善的电迁移寿命

    公开(公告)号:US20050186782A1

    公开(公告)日:2005-08-25

    申请号:US11090107

    申请日:2005-03-24

    摘要: A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.

    摘要翻译: 通过图案化第一电介质以形成金属线来形成双镶嵌互连结构。 第二电介质设置在第一电介质上并被图案化以形成通孔。 第一金属线以相对于通孔接合的结构进行图案化,使得当将进入第二电介质的通孔蚀刻延伸到第一电介质中时形成空腔。 在形成通孔的情况下,以一体的方式填充导电金属以形成通孔突起,以改善通孔和金属线之间的电接触。