公开(公告)号：US06777807B1

公开(公告)日：2004-08-17

申请号：US10448082

申请日：2003-05-29

申请人： Valeriy Sukharev ,  Wilbur G. Catabay ,  Hongqiang Lu

发明人： Valeriy Sukharev ,  Wilbur G. Catabay ,  Hongqiang Lu

IPC分类号： H01L2348

CPC分类号： H01L21/76849 ,  H01L21/7684 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

公开(公告)号：US06935933B1

公开(公告)日：2005-08-30

申请号：US10036621

申请日：2001-12-21

申请人： Valeriy Sukharev ,  Wilbur G. Catabay

发明人： Valeriy Sukharev ,  Wilbur G. Catabay

IPC分类号： B24B7/22 ,  C25F3/02 ,  H01L21/321 ,  H01L21/768

CPC分类号： H01L21/7684 ,  C25F3/02 ,  H01L21/32115

摘要： A method for planarizing a surface of an electrically conductive layer on a substrate, where the surface of the electrically conductive layer has relatively high features and relatively low features. A viscous material is applied to the surface of the electrically conductive layer, whereby at least the relatively low features are covered by the viscous material. The substrate is immersed in an electrically conductive solution. An electrical potential is applied between the electrically conductive layer and an electrode within the electrically conductive solution, whereby reaction kinetics favor erosion of the electrically conductive layer. The electrically conductive solution is agitated, thereby selectively uncovering the viscous material from at least features that are relatively high, and thereby preferentially planarizing at least the features that are relatively high.

摘要翻译： 一种用于平坦化基板上的导电层的表面的方法，其中导电层的表面具有相对较高的特征和相对较低的特征。 将粘性材料施加到导电层的表面，由此至少相对较低的特征被粘性材料覆盖。 将基板浸入导电溶液中。 在导电溶液中的导电层和电极之间施加电位，由此反应动力学有利于导电层的侵蚀。 搅动导电溶液，从而从至少相对高的特征选择性地露出粘性材料，从而优先至少平坦化至少相对高的特征。

公开(公告)号：US06686272B1

公开(公告)日：2004-02-03

申请号：US10020084

申请日：2001-12-13

申请人： Sang-Yun Lee ,  Masaichi Eda ,  Hongqiang Lu ,  Wei-Jen Hsia ,  Wilbur G. Catabay ,  Hiroaki Takikawa ,  Yongbae Kim

发明人： Sang-Yun Lee ,  Masaichi Eda ,  Hongqiang Lu ,  Wei-Jen Hsia ,  Wilbur G. Catabay ,  Hiroaki Takikawa ,  Yongbae Kim

IPC分类号： H01L214763

CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/0276 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/931 ,  Y10S438/952

摘要： The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.

摘要翻译： 本发明涉及碳化硅抗反射涂层（ARC）和碳氧化硅ARC。 另一个实施方案涉及用氧等离子体处理的碳氧化硅ARC。 本发明包括在半导体衬底表面上形成碳化硅层和碳氧化硅层作为ARC的方法实施例。 特别地，所述方法包括将甲基硅烷材料引入处理室中，其中它们被等离子体点燃并作为碳化硅沉积在基板表面上。 另一种方法包括将具有惰性载气的甲基硅烷前体材料用氧气引入到处理室中。 将这些材料点燃到等离子体中，并将​​碳氧化硅材料沉积到基底上。 通过调节氧气流速，可以调节碳硅氧烷层的光学性能。 在另一个实施方案中，可以用氧等离子体处理碳氧化硅层。

公开(公告)号：US07675177B1

公开(公告)日：2010-03-09

申请号：US11074456

申请日：2005-03-07

申请人： Hongqiang Lu ,  Byung-Sung Kwak ,  Wilbur G. Catabay

发明人： Hongqiang Lu ,  Byung-Sung Kwak ,  Wilbur G. Catabay

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76849 ,  H01L21/2885 ,  H01L21/76867 ,  H01L21/76877

摘要： A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.

摘要翻译： 通过在电介质层中形成沟槽，在镶嵌结构中形成具有Sn涂层的铜互连。 沟槽通过同时与金属掺杂剂电镀铜形成掺杂的铜层而形成。 掺杂铜层的顶层被还原成与第一介电层的表面形成平坦化的表面水平。 将掺杂的铜退火以驱动金属掺杂剂，以在掺杂铜层的平坦化顶表面上形成金属掺杂物覆盖涂层。

公开(公告)号：US06884720B1

公开(公告)日：2005-04-26

申请号：US10648602

申请日：2003-08-25

申请人： Hongqiang Lu ,  Byung-Sung Kwak ,  Wilbur G. Catabay

发明人： Hongqiang Lu ,  Byung-Sung Kwak ,  Wilbur G. Catabay

IPC分类号： H01L21/288 ,  H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/2885 ,  H01L21/76867 ,  H01L21/76877

摘要： A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.

摘要翻译： 通过在电介质层中形成沟槽，在镶嵌结构中形成具有Sn涂层的铜互连。 沟槽通过同时与金属掺杂剂电镀铜形成掺杂的铜层而形成。 掺杂铜层的顶层被还原成与第一介电层的表面形成平坦化的表面水平。 将掺杂的铜退火以驱动金属掺杂剂，以在掺杂铜层的平坦化顶表面上形成金属掺杂物覆盖涂层。

公开(公告)号：US08043968B2

公开(公告)日：2011-10-25

申请号：US12764004

申请日：2010-04-20

申请人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

发明人： Hao Cui ,  Peter A. Burke ,  Wilbur G. Catabay

IPC分类号： H01L21/00

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分提高的对铜的粘附性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

公开(公告)号：US06613665B1

公开(公告)日：2003-09-02

申请号：US10002981

申请日：2001-10-26

申请人： Wilbur G. Catabay ,  Wei-Jen Hsia

发明人： Wilbur G. Catabay ,  Wei-Jen Hsia

IPC分类号： H01L214763

CPC分类号： H01L21/31144 ,  H01L21/0276 ,  H01L21/76807 ,  H01L21/76826

摘要： A process is disclosed for forming an integrated circuit structure characterized by formation of a combined dielectric layer and antireflective coating layer. The process comprises forming a layer of dielectric material over an integrated circuit structure, and treating the surface of the layer of dielectric material to form an antireflective coating (ARC) surface therein. When a layer of photoresist is then formed over the ARC surface, and the layer of photoresist is exposed to a pattern of radiation, the ARC surface improves the accuracy of the replication, in the photoresist layer, of the pattern of radiation. Preferably, the surface of the dielectric layer is treated with a plasma comprising ions of elements and/or compounds to form the ARC surface.

摘要翻译： 公开了一种用于形成集成电路结构的方法，其特征在于形成组合的电介质层和抗反射涂层。 该方法包括在集成电路结构上形成介电材料层，以及处理介电材料层的表面以在其中形成抗反射涂层（ARC）表面。 当然后在ARC表面上形成一层光致抗蚀剂，并且光致抗蚀剂层暴露于辐射图形时，ARC表面提高了光致抗蚀剂层中辐射图案复制的准确性。 优选地，用包含元素和/或化合物的离子的等离子体处理介电层的表面以形成ARC表面。

公开(公告)号：US06204192B1

公开(公告)日：2001-03-20

申请号：US09281602

申请日：1999-03-29

申请人： Joe W. Zhao ,  Wei-Jen Hsia ,  Wilbur G. Catabay

发明人： Joe W. Zhao ,  Wei-Jen Hsia ,  Wilbur G. Catabay

IPC分类号： H01L2100

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76826

摘要： A process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more opening, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.

摘要翻译： 提供了一种用于从集成电路结构的铜金属互连层上去除在低介电常数绝缘材料的一层或多层中形成的一个或多个开口的蚀刻残留物的工艺，其包括清洁铜互连层的表面的暴露部分 在一个或多个开口的底部，该方法包括提供各向异性氢等离子体以引起等离子体中的离子与一个或多个开口底部的蚀刻残留物（包括暴露的铜表面上的氧化铜）的化学反应 ，从而清洁铜表面的暴露部分，并且在不溅射开口底部的铜的情况下除去蚀刻残留物。

公开(公告)号：US5994775A

公开(公告)日：1999-11-30

申请号：US932614

申请日：1997-09-17

申请人： Joe W. Zhao ,  Wilbur G. Catabay

发明人： Joe W. Zhao ,  Wilbur G. Catabay

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002

摘要： The invention comprises an integrated circuit structure, and a process for making same, comprising a via/contact opening in a dielectric layer; a CVD layer of titanium nitride having a thickness of at least about 50 Angstroms, but not exceeding about 200 Angstroms, on the sidewall and bottom surfaces of the via/contact opening to provide adherence of the filler material to the underlying and sidewall surface of the opening; a CVD barrier layer of tungsten, having a thickness of about 50 Angstroms, but not exceeding about 300 Angstroms, formed over the titanium nitride layer; and the remainder of the via/contact opening filled with a highly conductive metal selected from the group consisting of copper, CVD aluminum, and force-filled aluminum.

摘要翻译： 本发明包括集成电路结构及其制造方法，其包括介电层中的通孔/接触开口; 在通孔/接触开口的侧壁和底表面上具有至少约50埃但不超过约200埃的厚度的氮化钛的CVD层，以提供填充材料对下层和侧壁表面的附着 开口 在氮化钛层上形成厚度为约50埃，但不超过约300埃的钨的CVD阻挡层; 并且通孔/接触开口的其余部分填充有选自铜，CVD铝和强力填充铝的高导电性金属。

公开(公告)号：US5953631A

公开(公告)日：1999-09-14

申请号：US592870

申请日：1996-01-24

申请人： Joe W. Zhao ,  Wilbur G. Catabay

发明人： Joe W. Zhao ,  Wilbur G. Catabay

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76843

摘要： A method is presented for depositing a low stress, highly conformal metal thin film, such as tungsten, on a substrate. A substrate is provided, and is heated to a first temperature. A first portion of the metal thin film is deposited on the substrate by reacting a first set of process gases. The deposition of the first portion of the metal thin film is stopped after a first length of time, and the substrate is heated to a second temperature, which is greater than the first temperature. A second portion of the metal thin film is deposited on the substrate by reacting a second set of process gases. The second portion of the metal thin film comprises the same metal as the first portion of the metal thin film. The deposition of the second portion of the metal thin film is stopped after a second length of time. Semiconductor devices having a low stress, highly conformal thin film are also described.

摘要翻译： 提出了一种在衬底上沉积低应力，高保形金属薄膜（如钨）的方法。 提供基板，并加热至第一温度。 通过使第一组工艺气体反应，将金属薄膜的第一部分沉积在衬底上。 金属薄膜的第一部分的沉积在第一时间段之后停止，并且将基板加热到大于第一温度的第二温度。 金属薄膜的第二部分通过使第二组工艺气体反应而沉积在衬底上。 金属薄膜的第二部分包含与金属薄膜的第一部分相同的金属。 金属薄膜的第二部分的沉积在第二时间长度之后停止。 还描述了具有低应力，高保形薄膜的半导体器件。