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    MECHANICAL STRESS CHARACTERIZATION IN SEMICONDUCTOR DEVICE
    1.
    发明申请
    MECHANICAL STRESS CHARACTERIZATION IN SEMICONDUCTOR DEVICE 失效
    半导体器件中的机械应力特性

    公开(公告)号：US20070056380A1

    公开(公告)日：2007-03-15

    申请号：US11162295

    申请日：2005-09-06

    Applicant: Victor Chan ,  Khee Lim

    Inventor： Victor Chan ,  Khee Lim

    IPC: G01B7/16

    CPC classification number: G01R31/2648

    Abstract: Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer.

    Abstract translation: 公开了在晶体管的应力层中表征机械应力水平的方法和机械应力表征测试结构。 在一个实施例中，测试结构包括包括第一应力水平的第一测试晶体管; 以及至少一个具有基本上不同的第二应力水平的第二测试晶体管。 然后可以通过比较第一测试晶体管和至少一个第二测试晶体管的性能来测试电路来表征机械应力水平。 测试结构的类型取决于所使用的集成方案。 在一个实施例中，至少一个第二测试晶体管具有基本上中性的应力水平和/或与第一应力水平相反的应力水平。 基本中性的应力水平可以通过旋转晶体管来提供，去除施加应力的应力层，或者使应力层的应力层解除应力层。

    Double anneal with improved reliability for dual contact etch stop liner scheme
    2.
    发明申请
    Double anneal with improved reliability for dual contact etch stop liner scheme 有权
    双重退火，具有改进的双接触蚀刻停止衬垫方案的可靠性

    公开(公告)号：US20070138564A1

    公开(公告)日：2007-06-21

    申请号：US11304455

    申请日：2005-12-15

    Applicant: Khee Lim ,  Victor Chan ,  Eng Lim ,  Wenhe Lin ,  Jamin Fen

    Inventor： Khee Lim ,  Victor Chan ,  Eng Lim ,  Wenhe Lin ,  Jamin Fen

    IPC: H01L21/8238 ,  H01L29/78

    CPC classification number: H01L21/823807 ,  H01L21/3003 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823864 ,  H01L29/7843

    Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

    Abstract translation: 使用PFET压缩蚀刻停止衬垫和NFET拉伸蚀刻停止衬垫以及在含氘气氛中的两个退火来形成具有PFET和NFET晶体管的器件的方法。 该方法包括：在PFET区域中的NFET区域中提供NFET晶体管和PFET晶体管。 我们在NFET区域上形成NFET拉伸接触蚀刻停止衬垫。 然后我们进行第一次氘退火。 我们在PFET区域上形成PFET压电蚀刻停止衬垫。 我们在衬底上形成具有接触开口的（ILD）电介质层。 我们进行第二次氘退火。 第二次氘退火的温度小于第一次氘退火的温度。

    DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
    4.
    发明申请
    DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
    CMOS混合方向的双路隔离

    公开(公告)号：US20120104511A1

    公开(公告)日：2012-05-03

    申请号：US13349203

    申请日：2012-01-12

    Applicant: Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

    Inventor： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

    IPC: H01L27/092

    CPC classification number: H01L21/76229

    Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

    Abstract translation: 本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。 在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。 根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

    Database schema for content managed data
    6.
    发明授权
    Database schema for content managed data 有权
    内容管理数据的数据库模式

    公开(公告)号：US07505993B2

    公开(公告)日：2009-03-17

    申请号：US11304015

    申请日：2005-12-14

    Applicant: Victor Chan ,  Darl Andrew Crick ,  Miu-To Brenda Lam ,  Wan Ngai Wayne Lee ,  Jacob Vandergoot ,  Tony Chung Keung Woo

    Inventor： Victor Chan ,  Darl Andrew Crick ,  Miu-To Brenda Lam ,  Wan Ngai Wayne Lee ,  Jacob Vandergoot ,  Tony Chung Keung Woo

    IPC: G06F7/00 ,  G06F17/00

    CPC classification number: G06F17/30595 ,  Y10S707/99943 ,  Y10S707/99944

    Abstract: Embodiments of the present invention is directed to a data structure in conformance with a database schema for accessing and managing content managed data and to a system, a method and a computer program product for creating the database schema. According to one embodiment of the invention, a method for creating a database schema for accessing and managing content managed data comprising the steps of: creating a base schema; creating a write schema; and creating a read schema; the database schema used by a business logic application to access and manipulate the content managed data in the database. Embodiment of the present invention manages changes to the data using the write schema and the read schema rather than by using a modified base schema.

    Abstract translation: 本发明的实施例涉及一种符合用于访问和管理内容管理数据的数据库模式的数据结构以及用于创建数据库模式的系统，方法和计算机程序产品。 根据本发明的一个实施例，一种用于创建用于访问和管理内容管理数据的数据库模式的方法，包括以下步骤：创建基本模式; 创建一个写入模式; 并创建一个读模式; 业务逻辑应用程序使用的数据库模式来访问和操纵数据库中的内容管理数据。 本发明的实施例使用写模式和读模式管理对数据的改变，而不是使用经修改的基本模式。

    DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
    7.
    发明申请
    DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
    CMOS混合方向的双路隔离

    公开(公告)号：US20080290379A1

    公开(公告)日：2008-11-27

    申请号：US12169991

    申请日：2008-07-09

    Applicant: Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

    Inventor： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

    IPC: H01L21/8234 ,  H01L29/04

    CPC classification number: H01L21/76229

    Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

    Abstract translation: 本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。 在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。 根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

    INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED SPACERS
    8.
    发明申请
    INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED SPACERS 有权
    集成电路系统应用于工程应用的空间

    公开(公告)号：US20080173934A1

    公开(公告)日：2008-07-24

    申请号：US12048994

    申请日：2008-03-14

    Applicant: Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

    Inventor： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

    IPC: H01L27/092

    CPC classification number: H01L29/7833 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    Abstract: An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.

    Abstract translation: 一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。

    Method and system for composing a query for a database and traversing the database
    9.
    发明授权
    Method and system for composing a query for a database and traversing the database 有权
    用于组合数据库查询并遍历数据库的方法和系统

    公开(公告)号：US07401095B2

    公开(公告)日：2008-07-15

    申请号：US11246341

    申请日：2005-10-07

    Applicant: Victor Chan ,  Fen Wang ,  Mark W. Hubbard

    Inventor： Victor Chan ,  Fen Wang ,  Mark W. Hubbard

    IPC: G06F17/00

    CPC classification number: G06F17/30433 ,  G06F17/30477 ,  Y10S706/922 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99943 ,  Y10S707/99945

    Abstract: A system and method of composing a query object for application against a database is provided. The method composes a selection clause for the query. Next, a criteria clause for the query is generated, with the criteria clause comprising input criteria related to the query, additional criteria specified against the query, and generated criteria based on a joint relationship. Next a source clause utilizing elements in the database accessed by the query is generated. A database traversal system and method is provided. The method identifies all tables directly accessible by each table and creates a data structure comprising an entry for each table. The entry comprises an identification field for each table and a link field identifying all tables directly accessible by each table. The data structure is traversed and an optimum path of the traversal paths utilizing data obtained from traversing the data structure is identified.

    Abstract translation: 提供了一种组合用于数据库应用的查询对象的系统和方法。 该方法为查询组成一个选择子句。 接下来，生成查询的条件子句，其中条件子句包括与查询相关的输入条件，针对查询指定的附加条件以及基于联合关系生成的条件。 接下来，生成一个使用查询访问的数据库中的元素的源子句。 提供了数据库遍历系统和方法。 该方法识别每个表可以直接访问的所有表，并创建一个包含每个表的条目的数据结构。 条目包括每个表的标识字段和标识由每个表可直接访问的所有表的链接字段。 遍历数据结构，并且识别遍历数据结构获得的数据的遍历路径的最佳路径。

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