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    Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch
    1.
    发明授权
    Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch 有权

    公开(公告)号：US06528363B2

    公开(公告)日：2003-03-04

    申请号：US09811707

    申请日：2001-03-19

    申请人： Victor Ku ,  Maheswaran Surendra ,  Len Tsou ,  Ying Zhang

    发明人： Victor Ku ,  Maheswaran Surendra ,  Len Tsou ,  Ying Zhang

    IPC分类号： H01L21336

    CPC分类号： H01L29/42376 ,  H01L21/28114

    摘要： A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

    PROCESS OPTIONS OF FORMING SILICIDED METAL GATES FOR ADVANCED CMOS DEVICES
    5.
    发明申请
    PROCESS OPTIONS OF FORMING SILICIDED METAL GATES FOR ADVANCED CMOS DEVICES 失效
    用于高级CMOS器件形成硅化金属栅的工艺选择

    公开(公告)号：US20050064690A1

    公开(公告)日：2005-03-24

    申请号：US10605261

    申请日：2003-09-18

    申请人： Ricky Amos ,  Douglas Buchanan ,  Cyril Cabral ,  Evgeni Gousev ,  Victor Ku ,  An Steegen

    发明人： Ricky Amos ,  Douglas Buchanan ,  Cyril Cabral ,  Evgeni Gousev ,  Victor Ku ,  An Steegen

    IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L21/4763

    CPC分类号： H01L21/823842 ,  H01L21/76895 ,  H01L21/823835

    摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.

    摘要翻译： 硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。 将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或 现有的金属门。 硅化物用作连接CMOS结构的PFET和NFET器件的选项。 该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。 提供了具有栅极和源极和漏极区域的半导体衬底。 栅极电介质层与金属栅极层一起沉积在衬底上。 然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。 可以在栅极内使用第二硅化物。 在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

    Methods for fabricating dual material gate in a semiconductor device
    8.
    发明授权
    Methods for fabricating dual material gate in a semiconductor device 失效
    在半导体器件中制造双材料栅极结构的方法

    公开(公告)号：US07635648B2

    公开(公告)日：2009-12-22

    申请号：US12100557

    申请日：2008-04-10

    申请人： Igor Peidous ,  Victor Ku ,  Joe Piccirillo

    发明人： Igor Peidous ,  Victor Ku ,  Joe Piccirillo

    IPC分类号： H01L21/311

    CPC分类号： H01L29/78 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517

    摘要： A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode.

    摘要翻译： 提供了一种在器件中制造双材料栅极结构的方法。 双材料栅结构在器件的不同区域具有不同的栅电极材料。 在一个实施例中，该方法包括提供具有图案化的第一栅极电极和设置在衬底上的图案化的第一栅极介电层的衬底，从衬底去除第一栅电极的一部分以在衬底上限定沟槽，并填充 沟槽以形成第二栅电极。

    Process options of forming silicided metal gates for advanced CMOS devices
    9.
    发明申请
    Process options of forming silicided metal gates for advanced CMOS devices 有权

    公开(公告)号：US20060105515A1

    公开(公告)日：2006-05-18

    申请号：US11271032

    申请日：2005-11-10

    申请人： Ricky Amos ,  Douglas Buchanan ,  Cyril Cabral ,  Evgeni Gousev ,  Victor Ku ,  An Steegen

    发明人： Ricky Amos ,  Douglas Buchanan ,  Cyril Cabral ,  Evgeni Gousev ,  Victor Ku ,  An Steegen

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/76895 ,  H01L21/823835

    摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.