Superimposed displays
    3.
    发明授权
    Superimposed displays 有权
    叠加显示

    公开(公告)号:US08508434B2

    公开(公告)日:2013-08-13

    申请号:US11449516

    申请日:2006-06-07

    IPC分类号: G09G5/00

    摘要: Various embodiments of methods and systems for constructing, configuring, and utilizing displays constructed from superimposed display subunits are disclosed. In one aspect, a display includes a first display subunit including a first plurality of light modulating elements, a second display subunit including a second plurality of light modulating elements, an optical system configured to optically superimpose each light modulating element of the first plurality with a corresponding light modulating element of the second plurality, and electronic circuitry configured to control operation of light modulating elements in the first display subunit to compensate for defective light modulating elements in the second display subunit. Light modulating elements may modulate light in a respective characteristic patterns. Display subunits containing light modulating or light emitting elements may be superimposed physically or optically to form superimposed display elements. Superimposed display subunits may be configured to compensate for ‘bad’, non-functioning, or malfunctioning display elements. Electrical and optical components may be used to configure superimposed display elements.

    摘要翻译: 公开了用于构造,配置和利用由叠加的显示子单元构成的显示器的方法和系统的各种实施例。 一方面,显示器包括:第一显示单元,包括第一多个光调制元件;第二显示单元,包括第二多个光调制元件;光学系统,被配置为光学地将第一多个光调制元件与 以及电子电路,被配置为控制第一显示子单元中的光调制元件的操作,以补偿第二显示子单元中的有缺陷的光调制元件。 光调制元件可以调制相应特征图案中的光。 包含光调制或发光元件的显示子单元可以物理地或光学上叠加以形成叠加的显示元件。 叠加显示子单元可以被配置为补偿“坏”,不起作用或故障的显示元件。 电气和光学部件可以用于配置叠加的显示元件。

    Handling processor computational errors
    5.
    发明授权
    Handling processor computational errors 失效
    处理处理器计算错误

    公开(公告)号:US08375247B2

    公开(公告)日:2013-02-12

    申请号:US11364131

    申请日:2006-02-28

    IPC分类号: G06F11/00

    摘要: Embodiments include a computer processor-error controller, a computerized device, a device, an apparatus, and a method. A computer processor-error controller includes a monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction. The computer processor-error controller includes an error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.

    摘要翻译: 实施例包括计算机处理器 - 错误控制器,计算机化设备,设备,设备和方法。 计算机处理器错误控制器包括监视电路,其可操作以由处理器检测对应于执行第二指令的计算错误,所述处理器可操作以执行包括在所述第二指令之前获取的第一指令的程序指令序列。 计算机处理器错误控制器包括错误恢复电路,其可操作以响应于检测到的计算错误将程序指令序列的执行恢复到第一指令。

    Hardware-error tolerant computing
    7.
    发明授权
    Hardware-error tolerant computing 有权
    硬件容错计算

    公开(公告)号:US08255745B2

    公开(公告)日:2012-08-28

    申请号:US12319696

    申请日:2009-01-08

    IPC分类号: G06F11/00

    摘要: Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.

    摘要翻译: 实施例包括计算系统,设备和方法。 计算系统包括具有可调操作参数的处理器子系统。 计算系统还包括可操作以保存指令序列的信息存储器。 计算系统还包括控制器模块。 控制器模块包括监视器电路,用于检测由处理器子系统执行指令序列的指令所对应的操作参数引起的错误的入射。 控制器还包括一个控制电路,用于根据容错性能标准来调节可调节的操作参数。