公开(公告)号：US06818516B1

公开(公告)日：2004-11-16

申请号：US10629496

申请日：2003-07-29

申请人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  James R. B. Elmer

发明人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  James R. B. Elmer

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/31111

摘要： A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.

摘要翻译： 在基板上的集成电路中形成栅极结构的方法。 在基板上形成高k层，在高k层上形成栅电极层。 栅极电极层是图案化的。 使用离子注入工艺形成LDD区域，从而产生高k层的损坏部分。 去除高k层的损坏部分的第一部分，从而限定栅极结构，并留下高k层的损坏部分的剩余部分。 侧壁间隔件形成在栅极结构附近。 使用离子注入工艺形成源极/漏极区，从而进一步损坏高k层的损伤部分的剩余部分。 然后去除高k层的损坏部分的剩余部分。

公开(公告)号：US07553772B1

公开(公告)日：2009-06-30

申请号：US11046949

申请日：2005-01-31

申请人： Shiqun Gu ,  Wai Lo ,  Hong Lin

发明人： Shiqun Gu ,  Wai Lo ,  Hong Lin

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76814 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/3105 ,  H01L21/31662 ,  H01L21/3185

摘要： Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with said radicals.

摘要翻译： 工艺和设备提供从远程等离子体源产生的反应性基团，其接触衬底表面的一部分，同时与同一衬底表面的接触与局部激活与所述自由基接触的衬底表面的部分的光源。

公开(公告)号：US20060035455A1

公开(公告)日：2006-02-16

申请号：US10915719

申请日：2004-08-10

申请人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

公开(公告)号：US20050064716A1

公开(公告)日：2005-03-24

申请号：US10951646

申请日：2004-09-28

申请人： Hong Lin ,  Shiqun Gu ,  Wai Lo ,  James Elmer

发明人： Hong Lin ,  Shiqun Gu ,  Wai Lo ,  James Elmer

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L29/80 ,  H01L21/302 ,  H01L21/461 ,  H01L31/112

CPC分类号： H01L29/518 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/31111 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517

摘要： A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an in-situ plasma species that causes structural damage to the exposed portions of the high k layer. The structurally damaged exposed portions of the high k layer are wet etched to leave the high k gate insulation layer.

摘要翻译： 在基板上的集成电路中形成高k栅极绝缘层的方法。 将高k层沉积在衬底上，并用掩模图案以限定高k栅极绝缘层和高k层的暴露部分。 高k层的暴露部分经受原位等离子体物质，这导致对高k层的暴露部分的结构损伤。 高k层的结构损坏的暴露部分被湿蚀刻以留下高k栅极绝缘层。

公开(公告)号：US07259462B1

公开(公告)日：2007-08-21

申请号：US11419548

申请日：2006-05-22

申请人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur G. Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur G. Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

摘要翻译： 对形成集成电路的方法的改进。 形成蚀刻停止层以覆盖集成电路的前端处理层。 形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。 基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

公开(公告)号：US20060197193A1

公开(公告)日：2006-09-07

申请号：US11072158

申请日：2005-03-04

申请人： Shiqun Gu ,  Wai Lo ,  Hong Lin

发明人： Shiqun Gu ,  Wai Lo ,  Hong Lin

IPC分类号： H01L39/00

CPC分类号： H01L21/76838 ,  H01L21/76834 ,  H01L23/53285 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some embodiments, the electrically conductive interconnects are formed of a variety of different superconducting materials. In one embodiment, only the backend electrically conductive interconnects are formed of the superconducting material. In some embodiments no vias are formed of the superconducting material. The interconductor dielectric layers are preferably formed of silicon oxide, and sometimes all of the interconductor dielectric layers are formed of silicon oxide. The superconducting material is in some embodiments at least one of an organic compound such as a potassium doped buckminsterfullerene, a cesium doped buckminsterfullerene, and other carbon containing compounds, a metallic material such as an inter-metallic material like Nb—Ti alloys and other substances formed by alloying metals, and an inorganic compound such as YBa2Cu3O7-x, (Pb,Bi)2Sr2Ca2Cu3O10-x and its derivatives, HgBaCaCuO and its derivatives, and TI—Ba—Ca—Cu—O and its derivatives.

摘要翻译： 对由超导材料形成的导电互连的集成电路的改进。 以这种方式，可以使导电互连非常小，但仍然具有足够的导电性。 在各种实施例中，所有导电互连由超导材料形成。 在一些实施例中，导电互连由各种不同的超导材料形成。 在一个实施例中，只有后端导电互连由超导材料形成。 在一些实施例中，没有由超导材料形成通孔。 互导体电介质层优选由氧化硅形成，并且有时所有的互导电介质层均由氧化硅形成。 在一些实施方案中，超导材料是有机化合物，例如掺杂钾的巴克敏斯特富勒烯，掺杂铯的德克敏斯特富勒烯和其它含碳化合物中的至少一种，金属材料如诸如Nb-Ti合金的金属间材料和其它物质 由金属合金化而形成的无机化合物，例如YBa 2 N 3 O 7-x X，（Pb，Bi）2 Sr 2 O 2和其衍生物HgBaCaCuO及其衍生物 和TI-Ba-Ca-Cu-O及其衍生物。

公开(公告)号：US06746925B1

公开(公告)日：2004-06-08

申请号：US10397451

申请日：2003-03-25

申请人： Hong Lin ,  Shiqun Gu ,  Wai Lo ,  Jim Elmer

发明人： Hong Lin ,  Shiqun Gu ,  Wai Lo ,  Jim Elmer

IPC分类号： H01L21336

CPC分类号： H01L21/28247 ,  H01L21/32105

摘要： In a method of forming an integrated circuit device, sidewall oxides are formed by plasma oxidation on the patterned gate. This controls encroachment beneath a dielectric layer underlying the patterned gate. The patterned gate is oxidized using in-situ O2 plasma oxidation. The presence of the sidewall oxides minimizes encroachment under the gate edge.

摘要翻译： 在形成集成电路器件的方法中，通过等离子体氧化在图案化的栅极上形成侧壁氧化物。 这控制在图案化栅极下面的介电层下方的侵入。 图案化栅极使用原位氧等离子体氧化进行氧化。 侧壁氧化物的存在使栅极边缘下的侵蚀最小化。

公开(公告)号：US07341978B2

公开(公告)日：2008-03-11

申请号：US11072158

申请日：2005-03-04

申请人： Shiqun Gu ,  Wai Lo ,  Hong Lin

发明人： Shiqun Gu ,  Wai Lo ,  Hong Lin

IPC分类号： H01L33/00

CPC分类号： H01L21/76838 ,  H01L21/76834 ,  H01L23/53285 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some embodiments, the electrically conductive interconnects are formed of a variety of different superconducting materials. In one embodiment, only the backend electrically conductive interconnects are formed of the superconducting material. In some embodiments no vias are formed of the superconducting material. The interconductor dielectric layers are preferably formed of silicon oxide, and sometimes all of the interconductor dielectric layers are formed of silicon oxide. The superconducting material is in some embodiments at least one of an organic compound such as a potassium doped buckminsterfullerene, a cesium doped buckminsterfullerene, and other carbon containing compounds, a metallic material such as an inter-metallic material like Nb—Ti alloys and other substances formed by alloying metals, and an inorganic compound such as YBa2Cu3O7-x, (Pb,Bi)2Sr2Ca2Cu3O10-x and its derivatives, HgBaCaCuO and its derivatives, and TI—Ba—Ca—Cu—O and its derivatives.

摘要翻译： 对由超导材料形成的导电互连的集成电路的改进。 以这种方式，可以使导电互连非常小，但仍然具有足够的导电性。 在各种实施例中，所有导电互连由超导材料形成。 在一些实施例中，导电互连由各种不同的超导材料形成。 在一个实施例中，只有后端导电互连由超导材料形成。 在一些实施例中，没有由超导材料形成通孔。 互导体电介质层优选由氧化硅形成，并且有时所有的互导电介质层均由氧化硅形成。 在一些实施方案中，超导材料是有机化合物，例如掺杂钾的巴克敏斯特富勒烯，掺杂铯的德克敏斯特富勒烯和其它含碳化合物中的至少一种，金属材料如诸如Nb-Ti合金的金属间材料和其它物质 由金属合金化而形成的无机化合物，例如YBa 2 N 3 O 7-x X，（Pb，Bi）2 Sr 2 O 2和其衍生物HgBaCaCuO及其衍生物 和TI-Ba-Ca-Cu-O及其衍生物。

公开(公告)号：US07081406B2

公开(公告)日：2006-07-25

申请号：US10915719

申请日：2004-08-10

申请人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur G. Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur G. Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

摘要翻译： 对形成集成电路的方法的改进。 形成蚀刻停止层以覆盖集成电路的前端处理层。 形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。 基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

公开(公告)号：US07915122B2

公开(公告)日：2011-03-29

申请号：US11312849

申请日：2005-12-20

申请人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

发明人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

IPC分类号： H01L21/336

CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。