利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.015 秒)

    Self-aligned eetching process
    1.
    发明授权
    Self-aligned eetching process 有权
    自对准提取过程

    公开(公告)号：US06211091B1

    公开(公告)日：2001-04-03

    申请号：US09373318

    申请日：1999-08-12

    申请人： Wan-Yih Lien ,  Meng-Jaw Cherng

    发明人： Wan-Yih Lien ,  Meng-Jaw Cherng

    IPC分类号： H01L213056

    CPC分类号： H01L27/10855 ,  H01L21/31116 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885 ,  H01L28/84 ,  H01L28/90

    摘要： The invention describes a self-aligned etching process. A conductive layer and a first insulating layer are formed on a substrate in sequence, and then the conductive layer and the first insulating layer are patterned to form a plurality of stacks on desired regions. Subsequently, spacers are formed on sidewalls of each stack, and a stop layer is then formed on the substrate. A second insulating layer is formed on the substrate and is planarized. Portions of the second insulating layer are removed to form a plurality of openings and to expose portions of the stop layer located between spacers. The exposed stop layer is removed.

    摘要翻译： 本发明描述了自对准蚀刻工艺。 依次在基板上形成导电层和第一绝缘层，然后将导电层和第一绝缘层图案化以在期望的区域上形成多个堆叠。 随后，在每个堆叠的侧壁上形成间隔物，然后在衬底上形成停止层。 在基板上形成第二绝缘层并进行平面化。 去除第二绝缘层的部分以形成多个开口并暴露位于间隔件之间的停止层的部分。 暴露的停止层被去除。

    Method of forming a metal-insulator-metal capacitor structure in a copper damascene process sequence
    3.
    发明授权
    Method of forming a metal-insulator-metal capacitor structure in a copper damascene process sequence 有权
    铜镶嵌工艺顺序中形成金属 - 绝缘体 - 金属电容器结构的方法

    公开(公告)号：US06876027B2

    公开(公告)日：2005-04-05

    申请号：US10411346

    申请日：2003-04-10

    申请人： Wan-Yih Lien ,  Chii-Ming M. Wu

    发明人： Wan-Yih Lien ,  Chii-Ming M. Wu

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/108

    CPC分类号： H01L28/55 ,  H01L21/76802 ,  H01L28/60

    摘要： A method of forming a metal-oxide-metal (MIM), capacitor structure wherein the fabrication procedures used for the MIM capacitor structure are integrated into a process sequence used to form damascene type copper interconnect structures for CMOS type devices, has been developed. The process sequence features a copper damascene connector located overlying exposed portions of a semiconductor substrate, and underlying the MIM capacitor structure. The MIM capacitor structure, comprised a capacitor dielectric layer sandwiched between conductive capacitor plates, is protected during several selective reactive ion etching patterning procedures by an overlying anti-reflective coating (ARC), insulator shape, and by insulator spacers located on the sides of the ARC shape and on the sides of a capacitor dielectric shape. The presence of the insulator shape protects the MIM capacitor structure during a subsequent process used to define another copper damascene connector structure, overlying and contacting the MIM capacitor structure.

    摘要翻译： 已经开发了形成金属氧化物金属（MIM）电容器结构的方法，其中用于MIM电容器结构的制造程序集成到用于形成CMOS型器件的镶嵌型铜互连结构的工艺顺序中。 工艺顺序的特征在于铜镶嵌连接器位于半导体衬底的暴露部分的上方，并且位于MIM电容器结构之下。 包括夹在导电电容器板之间的电容器电介质层的MIM电容器结构在几个选择性反应离子蚀刻图案化步骤期间通过覆盖的抗反射涂层（ARC），绝缘体形状以及位于 ARC形状和电容器电介质形状的两侧。 绝缘体形状的存在在用于限定另一个铜镶嵌连接器结构的后续工艺中保护MIM电容器结构，覆盖并接触MIM电容器结构。

    Method for fabricating a high aspect ratio stacked contact hole
    4.
    发明授权
    Method for fabricating a high aspect ratio stacked contact hole 失效
    高比例堆叠接触孔的制造方法

    公开(公告)号：US6080664A

    公开(公告)日：2000-06-27

    申请号：US86771

    申请日：1998-05-29

    申请人： Sen-Huan Huang ,  Wan-Yih Lien ,  Yeur-Luen Tu

    发明人： Sen-Huan Huang ,  Wan-Yih Lien ,  Yeur-Luen Tu

    IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

    CPC分类号： H01L21/31144 ,  H01L21/76816

    摘要： A method for creating a metal filled, high aspect ratio, contact opening, in thick insulator layers, allowing contact between a metal interconnect structure and a region of a semiconductor substrate, has been developed. The process features creating a stacked contact hole opening, comprised of a upper contact hole opening, of a specific diameter size, overlying a lower contact hole opening, having an opening larger in diameter than the opening used for the upper contact hole opening. The lower contact hole opening is created via an anisotropic RIE procedure, followed by a wet etch procedure, used to enlarge the diameter of the lower contact hole opening. The upper contact hole opening, created using an anisotropic RIE procedure, is formed using the original diameter opening, used previously for the pre-wet etched, lower contact hole opening, and is easily aligned to a metal filled, enlarged lower contact hole opening.

    摘要翻译： 已经开发了一种用于在厚的绝缘体层中形成金属填充的高纵横比的接触开口，允许金属互连结构和半导体衬底的区域之间的接触的方法。 该过程的特征是产生一个堆叠的接触孔开口，包括比较直径尺寸的上接触孔开口，覆盖下接触孔开口，其开口直径大于用于上接触孔开口的开口。 通过各向异性RIE程序产生下接触孔开口，随后通过湿蚀刻程序，用于扩大下接触孔开口的直径。 使用各向异性RIE程序产生的上接触孔开口使用原来的直径开口形成，其预先用于预湿蚀刻的下接触孔开口，并且容易地与金属填充的扩大的下接触孔开口对准。

    Method of making local interconnections for dynamic random access memory (DRAM) circuits with reduced contact resistance and reduced mask set
    5.
    发明授权
    Method of making local interconnections for dynamic random access memory (DRAM) circuits with reduced contact resistance and reduced mask set 有权
    具有降低接触电阻和减少掩模集的动态随机存取存储器（DRAM）电路的局部互连的方法

    公开(公告)号：US6001717A

    公开(公告)日：1999-12-14

    申请号：US249258

    申请日：1999-02-12

    申请人： Wan-Yih Lien

    发明人： Wan-Yih Lien

    IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L21/28 ,  H01L21/336

    CPC分类号： H01L27/10894 ,  H01L21/76895

    摘要： A method for making low-resistance contacts between polycide layers for local interconnections is achieved. The method is particularly useful for making low contact resistance R.sub.c between the tungsten polycide layers for local interconnections on the periphery of the DRAM chip. A first polycide layer is patterned to form FET gate electrodes and portions of local interconnections. An interlevel dielectric layer is deposited over the patterned first polycide layer. Contact openings are etched in the dielectric layer to the surface of the substrate and to the first polycide layer. A second polycide layer is deposited and patterned to form bit lines in the memory cell areas of the DRAM, while concurrently forming local interconnections in the peripheral device areas. A high-temperature rapid thermal anneal (RTA) is carried out to substantially reduce the contact resistance in the contact openings over the first polycide layer in the peripheral areas. This RTA eliminates the need for overetching the first silicide in the contact holes, as commonly practiced in the prior art. The RTA of this invention with a traditional N.sub.2 anneal prior to the second polycide deposition results in a synergistic effect that further reduces the contact resistance R.sub.c.

    摘要翻译： 实现了用于局部互连的多晶硅层之间的低电阻接触的方法。 该方法特别适用于在DRAM芯片的周边上用于局部互连的多晶硅化钨层之间的低接触电阻Rc。 图案化第一多晶硅化物层以形成FET栅电极和局部互连的部分。 在图案化的第一多晶硅化物层上沉积层间电介质层。 电介质层中的接触开口被蚀刻到衬底的表面和第一多晶硅化物层。 沉积并图案化第二多晶硅层以在DRAM的存储单元区域中形成位线，同时在外围器件区域中形成局部互连。 进行高温快速热退火（RTA）以大大降低周边区域中的第一多晶硅化物层上的接触开口中的接触电阻。 该RTA消除了对现有技术中通常实施的接触孔中的第一硅化物的过蚀刻的需要。 本发明的RTA在第二次聚合物沉积之前具有传统的N2退火，从而产生进一步降低接触电阻Rc的协同效应。

    Dynamic random access memory with slanted active regions
    6.
    发明授权
    Dynamic random access memory with slanted active regions 有权
    具有倾斜活动区域的动态随机存取存储器

    公开(公告)号：US06303955B1

    公开(公告)日：2001-10-16

    申请号：US09439988

    申请日：1999-11-15

    申请人： Wan-Yih Lien ,  Meng-Jaw Cheng

    发明人： Wan-Yih Lien ,  Meng-Jaw Cheng

    IPC分类号： H01L27108

    CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10835 ,  Y10S257/907

    摘要： A structure of dynamic random access memory with slanted active regions, comprising: a substrate; a plurality of slanted active regions formed on the substrate, wherein each of the plurality of slanted active regions has a bit line contact; a plurality of word line regions formed on the substrate to control transistors of the dynamic random access memory; a plurality of bit line regions formed on the substrate, wherein each of the bit line regions cross the bit line contact hole so that the bit line contact hole is completely covered by the bit line regions; a plurality of capacitors formed between the plurality of bit line regions.

    摘要翻译： 具有倾斜有源区域的动态随机存取存储器的结构，包括：衬底; 形成在所述基板上的多个倾斜的有源区，其中所述多个倾斜的有源区中的每一个具有位线接触; 形成在所述基板上的多个字线区域，以控制所述动态随机存取存储器的晶体管; 形成在所述基板上的多个位线区域，其中每个所述位线区域与所述位线接触孔交叉，使得所述位线接触孔被所述位线区域完全覆盖; 形成在所述多个位线区域之间的多个电容器。

    Method for controlling the thickness of a passivation layer on a semiconductor device
    7.
    发明授权
    Method for controlling the thickness of a passivation layer on a semiconductor device 有权
    用于控制半导体器件上的钝化层的厚度的方法

    公开(公告)号：US6096579A

    公开(公告)日：2000-08-01

    申请号：US276260

    申请日：1999-03-25

    申请人： Wen-Shiang Liao ,  Wan-Yih Lien

    发明人： Wen-Shiang Liao ,  Wan-Yih Lien

    IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/525 ,  H01L21/82

    CPC分类号： H01L23/5258 ,  H01L21/31116 ,  H01L21/76802 ,  H01L2924/0002

    摘要： A method for controlling the thickness of a passivation layer underlying with a fuse on a semiconductor device is disclosed herein. The anti-reflective coating on a metal layer is buried in the passivation layer, and the fuse is in a semiconductor device. The method includes the following steps. First, use a first etchant and Ar to etch the passivation layer till the anti-reflective coating is exposed, the first thickness of the passivation layer above the anti-reflective coating is smaller than the second thickness of the passivation layer above the fuse. Then, utilize a second etchant to etch the anti-reflective coating till the metal layer is exposed. The second etchant has a selectivity ratio from the anti-reflective coating to the passivation layer being at least 10. The second etchant mentioned above includes BCl.sub.3, Cl.sub.2, O.sub.2, and Ar.

    摘要翻译： 本文公开了一种用于控制半导体器件上的熔丝下面的钝化层的厚度的方法。 金属层上的抗反射涂层被埋在钝化层中，并且熔丝处于半导体器件中。 该方法包括以下步骤。 首先，使用第一蚀刻剂和Ar蚀刻钝化层直到抗反射涂层露出，抗反射涂层上方的钝化层的第一厚度小于熔丝上方钝化层的第二厚度。 然后，利用第二蚀刻剂来蚀刻抗反射涂层，直到暴露金属层。 第二蚀刻剂具有从抗反射涂层到钝化层的选择比至少为10.上述第二蚀刻剂包括BCl 3，Cl 2，O 2和Ar。

    Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions
    8.
    发明授权
    Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions 有权
    用于制造具有离子注入的轻掺杂延伸区的场效应晶体管（FET）器件的镶嵌栅极电极方法

    公开(公告)号：US06673683B1

    公开(公告)日：2004-01-06

    申请号：US10291029

    申请日：2002-11-07

    申请人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

    发明人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

    IPC分类号： H01L21336

    CPC分类号： H01L29/66553 ,  H01L29/66545 ,  H01L29/6659

    摘要： A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.

    摘要翻译： 在半导体产品中形成场效应晶体管器件的方法当形成一对源极/漏极区域时首先使用图案化虚拟层作为离子注入掩模层，然后作为用于形成一对图案化牺牲层的心轴层， 限定对应于图案化虚拟层的线宽和位置的孔径。 然后在孔内自对准地形成一对牺牲间隔层和栅电极。 然后剥去一对图案化牺牲层和一对牺牲隔离层，并且使用栅电极作为用于离子注入的掩模，形成与半导体衬底内的一对源/漏区部分重叠的一对轻掺杂的延伸区。

    Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process
    9.
    发明授权
    Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process 有权
    使用双镶嵌工艺同时制造千兆位DRAM单元和周边互连结构的电容器结构的方法

    公开(公告)号：US6037216A

    公开(公告)日：2000-03-14

    申请号：US184342

    申请日：1998-11-02

    申请人： Hao-Chieh Liu ,  Fu-Liang Yang ,  Wan-Yih Lien ,  Tzu-Shih Yen

    发明人： Hao-Chieh Liu ,  Fu-Liang Yang ,  Wan-Yih Lien ,  Tzu-Shih Yen

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10844 ,  H01L27/10852

    摘要： A process for simultaneously forming storage node structures, for a DRAM cell, and an interconnect structure, for a peripheral region of a DRAM chip, has been developed. The process features the use of dual damascene procedures, with the first damascene procedure used to create the storage node, and interconnect structures, followed by a second damascene procedure, used to create plug structures, used to contact the underlying storage node and interconnect structures. This invention also features the use of SAC openings, allowing the formation of the SAC storage node structures to be realized.

    摘要翻译： 已经开发了用于DRAM芯片的外围区域的用于DRAM单元和互连结构的存储节点结构的处理。 该过程的特征在于使用双镶嵌程序，第一个镶嵌程序用于创建存储节点，以及互连结构，随后是用于创建用于接触底层存储节点和互连结构的插塞结构的第二镶嵌程序。 本发明还特征在于使用SAC开口，允许形成要实现的SAC存储节点结构。