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公开(公告)号：US5685070A
公开(公告)日：1997-11-11
申请号：US374979
申请日：1995-01-19
IPC分类号： H01L23/12 , H01L23/50 , H01L23/538 , H05K1/02 , H05K1/11 , H05K3/00 , H05K3/42 , H05K3/46 , H05K3/34
CPC分类号： H05K1/112 , H01L23/50 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H05K3/4602 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01087 , H01L2924/15173 , H05K2201/09472 , H05K2201/09509 , H05K2201/09518 , H05K2201/09536 , H05K2201/10674 , H05K2203/0207 , H05K2203/1394 , H05K2203/1581 , H05K3/0023 , H05K3/0044 , H05K3/0047 , H05K3/0094 , H05K3/4644 , H05K3/4652 , Y10T29/49126 , Y10T29/49144 , Y10T29/49165
摘要： A printed circuit board or card for direct chip attachment that includes at least one power core, at least one signal plane that is adjacent to the power core, and plated through holes for electrical connection is provided. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer. Photodeveloped blind vias for subsequent connection to the power core and drilled blind vias for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.
摘要翻译： 提供了一种用于直接芯片附接的印刷电路板或卡，其包括至少一个电源核心，与功率核心相邻的至少一个信号平面以及用于电连接的电镀通孔。 此外，电介质材料层与功率芯相邻，并且电路化的导电层与电介质材料相邻，随后是与导电层相邻的一层光敏电介质材料。 提供用于随后连接到电源核心的盲孔和用于后续连接到信号平面的钻孔盲孔。 还提供了用于制造用于直接芯片附接的印刷电路板或卡的工艺。
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公开(公告)号：US5672260A
公开(公告)日：1997-09-30
申请号：US633322
申请日：1996-04-17
申请人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
发明人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
CPC分类号： H01L24/81 , C25D5/022 , C25D5/08 , H01L21/4825 , H01L21/4853 , H05K3/241 , H05K3/3473 , H01L2224/11849 , H01L2224/119 , H01L2224/81193 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H05K2203/043 , H05K2203/054
摘要： Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.
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公开(公告)号：US06414509B1
公开(公告)日：2002-07-02
申请号：US09564652
申请日：2000-05-03
申请人： Anilkumar Chinuprasad Bhatt , Leo Raymond Buda , Robert Douglas Edwards , Paul Joseph Hart , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla , Richard Gerald Murphy , George John Saxenmeyer, Jr. , George Frederick Walker , Bette Jaye Whalen , Richard Stuart Zarr
发明人： Anilkumar Chinuprasad Bhatt , Leo Raymond Buda , Robert Douglas Edwards , Paul Joseph Hart , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla , Richard Gerald Murphy , George John Saxenmeyer, Jr. , George Frederick Walker , Bette Jaye Whalen , Richard Stuart Zarr
IPC分类号： G01R3102
CPC分类号： H01L24/81 , G01R31/2886 , H01L22/20 , H01L24/75 , H01L2224/0401 , H01L2224/05557 , H01L2224/13111 , H01L2224/75 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.
摘要翻译： 公开了半导体芯片的测试方法。 单个半导体芯片具有I / O，电源和接地触点。 在本发明的方法中，提供了一个芯片载体。 芯片载体具有对应于半导体芯片上的触点的触点。 载体触点具有树枝状表面。 芯片触点与芯片载体上的导体焊盘导电接触。 测试信号输入矢量被施加到半导体芯片的输入，从半导体芯片恢复输出信号矢量。 在测试之后，芯片可以从衬底去除。 或者，芯片可以在成功测试之后通过树枝状导体焊盘粘合到衬底上。
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公开(公告)号：US5656139A
公开(公告)日：1997-08-12
申请号：US585819
申请日：1996-01-16
申请人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
发明人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
CPC分类号： H01L24/81 , C25D5/022 , C25D5/08 , H01L21/4825 , H01L21/4853 , H05K3/241 , H05K3/3473 , H01L2224/11849 , H01L2224/119 , H01L2224/81193 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H05K2203/043 , H05K2203/054
摘要： Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.
摘要翻译： 可以通过在具有孔或凹槽（例如盲孔）的电介质层的表面上沉积导电材料层并且暴露于其中的导体和/或焊盘而形成具有高体积精度和形状均匀性的小的，紧密间隔的焊料材料沉积物 孔或凹槽，导电材料的掩模区域和另外的图案化介电层，将电镀焊料材料电镀到由掩模曝光的导电材料的区域上，通过选择性蚀刻和至少从至少 有孔电介质层的一部分表面。 盲孔内电镀的均匀性通过流体喷射和阴极搅拌的组合增强。 在电镀之前，可以通过在浸没池中用焊料材料的构成成分代替导体材料来避免所得到的焊料沉积物中的过多的导体材料。
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