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    TECHNIQUES FOR FORMING A CONTACT TO A BURIED DIFFUSION LAYER IN A SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    TECHNIQUES FOR FORMING A CONTACT TO A BURIED DIFFUSION LAYER IN A SEMICONDUCTOR MEMORY DEVICE 有权
    在半导体存储器件中形成接触扩散层的技术

    公开(公告)号：US20100224924A1

    公开(公告)日：2010-09-09

    申请号：US12717776

    申请日：2010-03-04

    Applicant: Wayne Ellis ,  John Kim

    Inventor： Wayne Ellis ,  John Kim

    IPC: H01L27/06

    CPC classification number: H01L27/1052 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/7841

    Abstract: Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer. The semiconductor memory device may also comprise an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. The semiconductor memory device may also comprise an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate.

    Abstract translation: 公开了用于在半导体存储器件中形成与埋入扩散层的接触的技术。 在一个特定的示例性实施例中，这些技术可以被实现为半导体存储器件。 半导体存储器件可以包括包括上层的衬底。 半导体存储器件还可以包括形成在衬底的上层上并以行和列布置的虚拟柱的阵列。 每个虚拟柱可以从上层向上延伸并且具有与衬底的上层电连接的底部接触。 半导体存储器件还可以包括形成在衬底的上层上并以行和列布置的活性柱的阵列。 每个有源支柱可以从上层向上延伸，并且具有活动的第一区域，活动的第二区域和活动的第三区域。 每个活性柱也可以与衬底的上层电连接。

    Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
    2.
    发明授权
    Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device 有权
    在半导体存储器件中形成与埋入扩散层的接触的技术

    公开(公告)号：US08710566B2

    公开(公告)日：2014-04-29

    申请号：US12717776

    申请日：2010-03-04

    Applicant: Wayne Ellis ,  John Kim

    Inventor： Wayne Ellis ,  John Kim

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L27/1052 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/7841

    Abstract: Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer. The semiconductor memory device may also comprise an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. The semiconductor memory device may also comprise an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate.

    Abstract translation: 公开了用于在半导体存储器件中形成与埋入扩散层的接触的技术。 在一个特定的示例性实施例中，这些技术可以被实现为半导体存储器件。 半导体存储器件可以包括包括上层的衬底。 半导体存储器件还可以包括形成在衬底的上层上并以行和列布置的虚拟柱的阵列。 每个虚拟柱可以从上层向上延伸并且具有与衬底的上层电连接的底部接触。 半导体存储器件还可以包括形成在衬底的上层上并以行和列布置的活性柱的阵列。 每个有源支柱可以从上层向上延伸，并且具有活动的第一区域，活动的第二区域和活动的第三区域。 每个活性柱也可以与衬底的上层电连接。

    SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS
    3.
    发明申请
    SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS 有权
    用于改进操作标准的SRAM电压控制

    公开(公告)号：US20070121370A1

    公开(公告)日：2007-05-31

    申请号：US11164556

    申请日：2005-11-29

    Applicant: Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    Inventor： Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    IPC: G11C11/00

    CPC classification number: G11C5/14 ,  G11C11/413

    Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

    Abstract translation: 提供了包括以阵列布置的多个SRAM单元的静态随机存取存储器（“SRAM”）。 阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的多个电压控制。 多个电压控制电路中的每一个耦合到电源的输出，每个电压控制电路具有临时降低提供给属于所选列列的多个SRAM单元的电源输入的电压的功能 SRAM。 选择的列被选择，并且在将位写入属于所选列的SRAM单元之一的写操作期间，该列的电源电压减小。

    SRAM voltage control for improved operational margins
    5.
    发明申请
    SRAM voltage control for improved operational margins 有权

    公开(公告)号：US20080089116A1

    公开(公告)日：2008-04-17

    申请号：US11998948

    申请日：2007-12-03

    Applicant: Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    Inventor： Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C5/14 ,  G11C11/413

    Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.

    Snap hook
    6.
    外观设计
    Snap hook 有权

    公开(公告)号：USD680420S1

    公开(公告)日：2013-04-23

    申请号：US29409968

    申请日：2011-12-30

    Applicant: Wayne Ellis

    Designer： Wayne Ellis

    Techniques for providing a direct injection semiconductor memory device
    7.
    发明授权
    Techniques for providing a direct injection semiconductor memory device 有权
    提供直接注入半导体存储器件的技术

    公开(公告)号：US08315099B2

    公开(公告)日：2012-11-20

    申请号：US12844477

    申请日：2010-07-27

    Applicant: Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    Inventor： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    IPC: G11C16/04

    CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

    Abstract translation: 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。 多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。 多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。 多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一 其他。

    TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE 有权
    提供直接注入半导体存储器件的技术

    公开(公告)号：US20110019482A1

    公开(公告)日：2011-01-27

    申请号：US12844477

    申请日：2010-07-27

    Applicant: Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    Inventor： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    IPC: G11C16/04

    CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

    Abstract translation: 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。 多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。 多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。 多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一 其他。

    Integrated Redundancy Architecture and Method for Providing Redundancy Allocation to an Embedded Memory System
    9.
    发明申请
    Integrated Redundancy Architecture and Method for Providing Redundancy Allocation to an Embedded Memory System 失效
    集成冗余架构和方法为嵌入式存储系统提供冗余分配

    公开(公告)号：US20050160310A1

    公开(公告)日：2005-07-21

    申请号：US10707797

    申请日：2004-01-13

    Applicant: Wayne Ellis ,  Kevin Gorman

    Inventor： Wayne Ellis ,  Kevin Gorman

    IPC: G06F11/00 ,  G11C29/00 ,  G11C29/44

    CPC classification number: G11C29/44 ,  G11C29/4401 ,  G11C29/74

    Abstract: An integrated redundancy architecture for an embedded memory system whereby a third memory element is added to the redundancy architecture such that all row and column fails may be stored in real-time. Architecture (20) includes a first memory element (22) (FME 22) having a register (24), a second memory element (26) (SME 26) having a register (28), a third memory element (30) (TME 30) having a register (32), and a finite state machine (34) (FSM 34) having a decision algorithm (36). FME (22), SME (26), TME (30), and FSM (34) are electrically connected to a built-in self-test (BIST) module (38). BIST module (38) outputs failed row and column addresses (40), also referred to as “fails,” for rows and columns that are identified as defective during the BIST to the memory elements and FSM (34). FSM (34) allocates redundancy resources of the memory system according to decision algorithm (36).

    Abstract translation: 用于嵌入式存储器系统的集成冗余架构，由此第三存储器元件被添加到冗余架构，使得可以实时地存储所有行和列失败。 架构（20）包括具有寄存器（24）的第一存储器元件（22）（FME 22），具有寄存器（28）的第二存储元件（26）（SME 26），第三存储器元件（30） 具有寄存器（32）和具有判定算法（36）的有限状态机（34）（FSM 34）。 FME（22），SME（26），TME（30）和FSM（34）电连接到内置自检（BIST）模块（38）。 对于在存储元件和FSM（34）的BIST期间被识别为有缺陷的行和列，BIST模块（38）输出失败的行和列地址（40），也称为“失败”。 FSM（34）根据决策算法（36）分配存储器系统的冗余资源。

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