公开(公告)号：US5861329A

公开(公告)日：1999-01-19

申请号：US764254

申请日：1996-12-12

申请人： Wen-Kuan Yeh ,  Coming Chen ,  Meng-Jin Tsai ,  Jih-Wen Chou

发明人： Wen-Kuan Yeh ,  Coming Chen ,  Meng-Jin Tsai ,  Jih-Wen Chou

IPC分类号： H01L21/28 ,  H01L21/318 ,  H01L21/336 ,  H01L29/49 ,  H01L21/265 ,  H01L21/31

CPC分类号： H01L29/6659 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/28176 ,  H01L21/3185 ,  H01L29/4983 ,  H01L29/6656

摘要： A method of fabricating a metal-oxide semiconductor (MOS) transistor is provided. This method is devised particularly to reduce the level of degradation to the MOS transistor caused by hot carriers. In the fabrication process, a plasma treatment is applied to the wafer to as to cause the forming of a thin layer of silicon nitride on the wafer which covers the gate and the lightly-doped diffusion (LDD) regions on the source/drain regions of the MOS transistor. This thin layer of silicon nitride acts as a barrier which prevents hot carriers from crossing the gate dielectric layer, such that the degradation of the MOS transistor due to hot carriers crossing the gate dielectric layer can be greatly minimized.

摘要翻译： 提供一种制造金属氧化物半导体（MOS）晶体管的方法。 该方法特别设计用于降低由热载流子引起的对MOS晶体管的劣化程度。 在制造过程中，对晶片施加等离子体处理，以便在覆盖栅极的晶片和在源极/漏极区上的轻掺杂扩散（LDD）区域上形成氮化硅薄层 MOS晶体管。 该氮化硅薄层作为阻止热载流子与栅极介电层交叉的阻挡层，从而可以极大地最小化由于与跨越栅极电介质层的热载流子导致的MOS晶体管的劣化。

公开(公告)号：US20110189854A1

公开(公告)日：2011-08-04

申请号：US13087356

申请日：2011-04-14

申请人： Kun-Lin Wu ,  Meng-Jin Tsai

发明人： Kun-Lin Wu ,  Meng-Jin Tsai

IPC分类号： H01L21/768

CPC分类号： H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

摘要： A chemical-mechanical polishing process includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

摘要翻译： 化学机械抛光工艺包括以下步骤：提供其上具有第一导电线的半导体衬底，然后在衬底和第一导电线上形成至少一个电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成覆盖层。 形成盖层的方法包括使用硅烷（SiH4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅酸氢钠（SiH 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，通过介电层和盖层形成通孔，以及通过通路孔与第一导电线电连接的第二导线。

公开(公告)号：US6077784A

公开(公告)日：2000-06-20

申请号：US132876

申请日：1998-08-11

申请人： Kun-Lin Wu ,  Meng-Jin Tsai

发明人： Kun-Lin Wu ,  Meng-Jin Tsai

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76829 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/7684

摘要： A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 .ANG. can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2 Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

摘要翻译： 用于形成金属互连的化学机械抛光工艺包括以下步骤：提供其上具有第一金属线的半导体衬底，然后在衬底和第一金属线上形成电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成薄盖层。 具有1000-3000厚度的薄盖层可以是例如二氧化硅层，磷硅酸盐玻璃层或富硅氧化物层。 形成盖层的方法包括使用硅烷（SiH4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅酸氢钠（SiH 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，形成通过介电层和盖层的通路开口，并且形成通过通路孔与第一金属线电连接的第二金属线。

公开(公告)号：US06251748B1

公开(公告)日：2001-06-26

申请号：US09165257

申请日：1998-10-01

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A method of manufacturing shallow trench isolation structure comprising the steps of forming a polysilicon mask layer over a substrate, and then patterning the polysilicon mask layer and the substrate to form a trench. Thereafter, a silicon nitride layer is formed covering the sidewalls of the trench. Next, a high-density chemical vapor deposition method is used to deposit oxide material into the trench. Finally, the surface is polished to remove a portion of the oxide layer and the silicon nitride layer until the polysilicon mask layer is exposed. The shallow trench isolation structure can avoid subthreshold kink effect and reduce subthreshold leakage current.

摘要翻译： 一种制造浅沟槽隔离结构的方法，包括以下步骤：在衬底上形成多晶硅掩模层，然后构图多晶硅掩模层和衬底以形成沟槽。 此后，形成覆盖沟槽的侧壁的氮化硅层。 接下来，使用高密度化学气相沉积方法将氧化物材料沉积到沟槽中。 最后，抛光该表面以去除氧化物层和氮化硅层的一部分，直到暴露多晶硅掩模层。 浅沟槽隔离结构可以避免亚阈值扭结效应，降低亚阈值漏电流。

公开(公告)号：US06001735A

公开(公告)日：1999-12-14

申请号：US110545

申请日：1998-07-06

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： H01L21/302 ,  H01L21/027 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76807

摘要： A method of forming a dual damascene structure includes forming an oxide layer and a mask layer there on, which both have protuberances over the conductive layers. Then a chemical mechanical polishing is performed to remove the protuberances and to form openings. The protuberances are above the conductive layers.

摘要翻译： 形成双镶嵌结构的方法包括在其上形成氧化物层和掩模层，两者都具有在导电层上的突起。 然后进行化学机械抛光以去除突起并形成开口。 突起在导电层之上。

公开(公告)号：US5981353A

公开(公告)日：1999-11-09

申请号：US798154

申请日：1997-02-10

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of making a shallow trench isolation region which has a reduced kink effect at a subthreshold voltage by forming a shallow trench isolation region, including providing a silicon substrate having a front surface and a backside surface. A first pad oxide layer is c formed over the front surface, and a second pad oxide layer is currently formed over the backside surface. A first silicon nitride layer is formed over the first pad oxide layer, and a second silicon nitride layer is concurrently formed over the second pad oxide layer. The first silicon nitride layer, first pad oxide layer, and the silicon substrate are patterned to form a trench. A side-wall oxide layer is formed within the trench, and a first oxide layer is concurrently formed on a surface of the second silicon nitride layer. A second oxide layer is formed over the first silicon nitride layer and fills the trench. The first oxide layer is removed, and a portion of the second oxide layer is removed. The first silicon nitride layer and the second silicon nitride layer are removed. The removal of the first oxide layer and the subsequent steps are performed in sequence.

摘要翻译： 一种形成浅沟槽隔离区域的方法，该区域通过形成浅沟槽隔离区域而在亚阈值电压下具有降低的扭结效应，包括提供具有前表面和背面的硅衬底。 在前表面上形成第一衬垫氧化物层，并且第二衬垫氧化物层当前形成在背面上。 在第一焊盘氧化物层上形成第一氮化硅层，并且在第二焊盘氧化物层上同时形成第二氮化硅层。 将第一氮化硅层，第一焊盘氧化物层和硅衬底图案化以形成沟槽。 在沟槽内形成侧壁氧化物层，并且在第二氮化硅层的表面上同时形成第一氧化物层。 第二氧化物层形成在第一氮化硅层上并填充沟槽。 去除第一氧化物层，并且去除一部分第二氧化物层。 去除第一氮化硅层和第二氮化硅层。 依次进行第一氧化物层的除去和后续步骤。

公开(公告)号：US5712185A

公开(公告)日：1998-01-27

申请号：US636623

申请日：1996-04-23

申请人： Meng-Jin Tsai ,  Water Lur ,  Chin-Lai Chen

发明人： Meng-Jin Tsai ,  Water Lur ,  Chin-Lai Chen

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/32 ,  H01L21/76224

摘要： A method for forming shallow trench isolation without a recessed edge problem is disclosed. The present invention comprises forming a pad oxide layer on a substrate. Next, a silicon nitride layer is formed on the pad oxide, and a sacrificial layer is formed on the silicon nitride layer. A photo-resist layer that defines an active region on the sacrificial layer is applied. Thereafter, the portions of the sacrificial layer, the silicon nitride layer, the pad oxide layer and the substrate are removed to form a trench. Portions of the silicon nitride layer are undercut, and a dielectric layer is formed to fill the trench. The dielectric layer is planarized until the silicon nitride layer is exposed. Finally, the silicon nitride layer and the pad oxide layer are removed.

摘要翻译： 公开了一种用于形成没有凹陷边缘问题的浅沟槽隔离的方法。 本发明包括在衬底上形成衬垫氧化物层。 接下来，在衬垫氧化物上形成氮化硅层，在氮化硅层上形成牺牲层。 施加在牺牲层上限定有源区的光致抗蚀剂层。 此后，去除牺牲层，氮化硅层，衬垫氧化物层和衬底的部分以形成沟槽。 底切部分的氮化硅层，形成电介质层以填充沟槽。 平坦化电介质层，直至暴露氮化硅层。 最后，去除氮化硅层和衬垫氧化物层。

公开(公告)号：US20060084259A1

公开(公告)日：2006-04-20

申请号：US11245175

申请日：2005-10-07

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： H01L21/60

CPC分类号： H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01075 ,  H01L2924/14

摘要： A manufacturing method of wafer passivation layer and manufacturing method of wafer bump. First, a wafer is provided with an active surface, which has a passivation layer and reveals a plurality of bonding pads on said passivation. Next, a redistribution layer is formed on the wafer and is electrically connected with the bonding pad. Further, a dielectric layer is formed on the wafer to cover the redistribution layer. Then, said dielectric layer is cured, followed by a patterning process, so that part of the redistribution layer can be revealed from the passivation. Next, plasma cleaning is performed on the active surface of the wafer, and the dielectric layer is cured again. Further, a bumping process is performed. This manufacturing method of wafer passivation and manufacturing method of wafer bump can effectively reduce potential damages of the passivation in further processing procedures and enhance yields.

摘要翻译： 晶圆钝化层的制造方法及晶圆凸块的制造方法。 首先，晶片设置有活性表面，其具有钝化层并且在所述钝化上显露多个键合焊盘。 接下来，在晶片上形成再分配层，并且与接合焊盘电连接。 此外，在晶片上形成介电层以覆盖再分布层。 然后，使所述电介质层固化，然后进行图案化处理，从而可以从钝化中显露部分再分布层。 接着，对晶片的活性表面进行等离子体清洗，再次固化电介质层。 此外，进行碰撞处理。 晶片钝化的制造方法和晶片凸块的制造方法可以在进一步的处理过程中有效地减少钝化的潜在损害并提高产量。

公开(公告)号：US06190983B1

公开(公告)日：2001-02-20

申请号：US09430278

申请日：1999-10-29

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： H01L21336

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L29/6659

摘要： A method for providing triangle shapes of high-density plasma CVD film, thereby the grad and source/drain implantation can be applied in the same step, and an offset source/drain mask layer can be eliminated. A substrate is provided incorporating a device, wherein the device is defined as a high-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxides is spaced from another of the field oxides by a high-voltage MOS region. Then, a gate oxide layer is formed above the silicon substrate. Moreover, a polysilicon layer is deposited over the gate oxide layer. A photoresist layer is formed above the polysilicon layer and gate oxide layer, wherein the photoresist layer is defined and etched to form a gate. Then, the photoresist layer is removed. Consequentially, a dielectric layer is deposited and etched above the polysilicon layer by using high-density plasma CVD to result in the inherit triangle shape of high-density plasma CVD film characteristic. N-type ions are implanted into the silicon substrate to form N-type grad therein, and then N+-type ions only penetrate through the flat high-density plasma CVD dielectric film and not the triangle shape high-density plasma CVD film to form source/drain regions inside the N-type grad.

摘要翻译： 一种用于提供高密度等离子体CVD膜的三角形形状的方法，从而可以在相同的步骤中施加渐变和源极/漏极注入，并且可以消除偏移源极/漏极掩模层。 提供了一种结合有器件的衬底，其中该器件被定义为高电压MOS区。 接下来，在基板上形成多个场氧化物，其中一个场氧化物通过高压MOS区与另一个场氧化物隔开。 然后，在硅衬底上形成栅极氧化层。 此外，在栅极氧化物层上沉积多晶硅层。 在多晶硅层和栅极氧化物层上方形成光致抗蚀剂层，其中光致抗蚀剂层被限定和蚀刻以形成栅极。 然后，除去光致抗蚀剂层。 因此，通过使用高密度等离子体CVD沉积和蚀刻多晶硅层之上的电介质层以产生高密度等离子体CVD膜特性的继承三角形形状。 将N型离子注入到硅衬底中以形成N型渐变，然后N +型离子仅穿透扁平高密度等离子体CVD电介质膜而不是三角形形状的高密度等离子体CVD膜形成源 /漏区内N型梯度。

公开(公告)号：US6156640A

公开(公告)日：2000-12-05

申请号：US115184

申请日：1998-07-14

申请人： Meng-Jin Tsai ,  Yimin Huang

发明人： Meng-Jin Tsai ,  Yimin Huang

IPC分类号： H01L21/027 ,  H01L21/768

CPC分类号： H01L21/76807 ,  H01L21/0276 ,  H01L21/76802 ,  H01L21/7684

摘要： A method for improving the damascene process window for metallization utilizes an anti-reflective coating to increase the precision of the photolithography process. An inter-layer dielectric and an anti-reflective layer are formed in turn on a semiconductor substrate. The inter-layer dielectric is patterned to form the interconnecting line regions. A conductive layer is then deposited on the semiconductor substrate and fills the interconnecting line regions. The chemical mechanical polish is performed to remove a portion of the conductive layer exceeding the interconnect line regions and simultaneously remove residual portion of said anti-reflective layer.

摘要翻译： 用于改进用于金属化的镶嵌工艺窗口的方法利用抗反射涂层来提高光刻工艺的精度。 依次在半导体衬底上形成层间电介质和抗反射层。 将层间电介质图案化以形成互连线区域。 然后将导电层沉积在半导体衬底上并填充互连线区域。 执行化学机械抛光以去除超过互连线区域的导电层的一部分，并同时去除所述抗反射层的残留部分。