公开(公告)号：US5611046A

公开(公告)日：1997-03-11

申请号：US978369

申请日：1992-11-18

申请人： William C. Russell ,  Andrew J. Kraslavsky ,  Robert D. Wadsworth ,  Lorraine F. Barrett ,  George A. Kalwitz ,  Tony K. Ip ,  Walter D. Kuver

发明人： William C. Russell ,  Andrew J. Kraslavsky ,  Robert D. Wadsworth ,  Lorraine F. Barrett ,  George A. Kalwitz ,  Tony K. Ip ,  Walter D. Kuver

IPC分类号： B41J29/38 ,  G06F3/12 ,  G06F13/00 ,  G06F13/12

CPC分类号： G06F13/128 ,  G06F3/1204 ,  G06F3/1207 ,  G06F3/1229 ,  G06F3/1259 ,  G06F3/1286 ,  G06F3/1288

摘要： Method and apparatus for interfacing a printer to a local area network includes the use of an interactive network board coupling the printer to the LAN. A bi-directional printer interface is disposed on the board and transmits print data to the printer, and receives printer status data from the printer. ALAN interface is disposed on the board for receiving print job information and printer status requests from the LAN, and for transmitting printer status information to the LAN. A ROM is disposed on the board and stores (i) application programs which receive the print job information and transmit the print data to the printer, and (ii) status and control programs which receive the printer status requests from the LAN, receive printer status data from the printer, transmit the printer status information to the LAN, and receive control information from the LAN and transmit it to the printer. A processor disposed on the board executes both the application programs and the status and control programs. Preferably, the application programs are selectively capable of placing the network board into a plurality of different printer configurations.

摘要翻译： 将打印机连接到局域网的方法和装置包括使用将打印机耦合到LAN的交互网板。 双面打印机接口设置在板上，并将打印数据传送到打印机，并从打印机接收打印机状态数据。 ALAN接口设置在板上用于从LAN接收打印作业信息和打印机状态请求，并将打印机状态信息发送到LAN。 一个ROM被放置在电路板上并存储（i）接收打印作业信息并将打印数据发送到打印机的应用程序，以及（ii）从LAN接收打印机状态请求的状态和控制程序，接收打印机状态 来自打印机的数据，将打印机状态信息发送到LAN，并从LAN接收控制信息并将其传送到打印机。 布置在板上的处理器执行应用程序和状态和控制程序。 优选地，应用程序选择性地能够将网络板放置在多个不同的打印机配置中。

公开(公告)号：US06438604B1

公开(公告)日：2002-08-20

申请号：US09166487

申请日：1998-10-05

申请人： Walter D. Kuver ,  Osman Ozay Oktay ,  Gregory F. Beck ,  Wei Zhou ,  Robert D. Wadsworth ,  Elias Montenegro ,  Tony K. Ip ,  Royce Earle Slick ,  Don Francis Purpura ,  Trent Lee England

发明人： Walter D. Kuver ,  Osman Ozay Oktay ,  Gregory F. Beck ,  Wei Zhou ,  Robert D. Wadsworth ,  Elias Montenegro ,  Tony K. Ip ,  Royce Earle Slick ,  Don Francis Purpura ,  Trent Lee England

IPC分类号： G06F1300

CPC分类号： H04L12/40058 ,  H04L12/40097 ,  H04L12/40117 ,  H04L29/06 ,  H04L29/06027 ,  H04L47/10 ,  H04L47/22 ,  H04L65/403 ,  H04L65/4076 ,  H04L65/607 ,  H04L65/80 ,  H04N7/147 ,  H04N7/148 ,  H04N21/4363 ,  H04N21/43632 ,  H04N21/64322 ,  H04N21/64707

摘要： A digital video network interface for transferring isochronous video data over an asynchronous local area network, including an isochronous interface for transmitting digital video data isochronously, a memory comprising first and second buffers for storing the isochronous video data, a network interface for transmitting video data from either the first or second buffers over the asynchronous local area network, and a memory buffer manager for controlling the output of the video data over the asynchronous local area network and for controlling the input/output of video data into/from the first or second buffers, wherein, when either the first or second buffers is filled with video data, the memory buffer manager shifts the input of data into an empty buffer and begins outputting video data to the asynchronous local area network from a filled buffer, upon receiving access to the local area network. Complementary ones of such video network interfaces may be provided on a network so as to permit one-way video streaming (to one or more receiving sites) or two-way video conferencing with network interfaces operating in full-duplex mode.

摘要翻译： 一种用于通过异步局域网传输同步视频数据的数字视频网络接口，包括用于同步地传输数字视频数据的同步接口，包括用于存储同步视频数据的第一和第二缓冲器的存储器，用于从 无论是在异步局域网上的第一或第二缓冲器，以及存储器缓冲管理器，用于控制异步局域网上的视频数据的输出，并用于控制视频数据输入/输出到第一或第二缓冲器 ，其中当所述第一或第二缓冲器中的任何一个被视频数据填充时，所述存储器缓冲器管理器将所述数据的输入移动到空的缓冲器中，并且当接收到所述第一或第二缓冲器的访问时，开始从填充的缓冲器向所述异步局域网输出视频数据 局域网。 可以在网络上提供这些视频网络接口的补充，以允许以全双工模式操作的网络接口进行单向视频流（到一个或多个接收站点）或双向视频会议。

公开(公告)号：US5701411A

公开(公告)日：1997-12-23

申请号：US336662

申请日：1994-11-04

申请人： Duc Tran ,  Robert D. Wadsworth ,  Tony K. Ip ,  William C. Russell

发明人： Duc Tran ,  Robert D. Wadsworth ,  Tony K. Ip ,  William C. Russell

IPC分类号： G06F13/00 ,  G06F13/40 ,  G06F11/20

CPC分类号： G06F13/4022

摘要： A network communication device has plural different connectors, each connectable to a network, and is capable of automatically selecting between the different connectors for network communication. A selector responsive to a selection signal selects one of the plural connectors, and a plurality of detectors, each associated with a corresponding connector, detects whether its corresponding connector is connected to the network. A processor executes a selection process by outputting a selection signal so as to select, in turn, each of the plural different connectors starting with a first connector, maintaining the state of the selection signal in a case where the detector associated with the selected connector indicates connection to the network, cycling to the next connector in a case where the detector does not indicate connection to the network, and repeating the selection process in a case where said processor has cycled through all of said plural connectors.

摘要翻译： 网络通信设备具有多个不同的连接器，每个连接器可连接到网络，并且能够在不同连接器之间自动选择网络通信。 响应于选择信号的选择器选择多个连接器中的一个，并且每个与相应连接器相关联的多个检测器检测其对应的连接器是否连接到网络。 处理器通过输出选择信号来执行选择处理，从而从第一连接器开始选择多个不同连接器中的每一个，在与所选择的连接器相关联的检测器指示的情况下保持选择信号的状态 连接到网络，在检测器未指示与网络的连接的情况下循环到下一个连接器，并且在所述处理器循环穿过所有多个连接器的情况下重复该选择过程。

公开(公告)号：US5606671A

公开(公告)日：1997-02-25

申请号：US336102

申请日：1994-11-04

申请人： Robert D. Wadsworth ,  Tony K. Ip ,  Daniel A. Danknick ,  William C. Russell

发明人： Robert D. Wadsworth ,  Tony K. Ip ,  Daniel A. Danknick ,  William C. Russell

IPC分类号： G06F11/273 ,  G06F13/24 ,  G06F13/00

CPC分类号： G06F11/2294 ,  G06F13/24

摘要： A serial port which transmits a start bit of a serial transmission to a non-maskable interrupt terminal of a microprocessor so as to be certain that the microprocessor responds to serial communication. The serial port includes a microprocessor-writable transmit bit connected to the transmit terminal of the serial port, a microprocessor-readable receive bit connected to the receive terminal of the serial port, and an NMI enable switch connected between the receive terminal and the NMI pin of the microprocessor. In a receive mode, the NMI enable switch which initially is in a conductive state, transmits the start bit of serial transmissions directly to the NMI pin of the microprocessor causing the microprocessor to interrupt on-going processes. The microprocessor disables the NMI enable register and, after waiting for serial transmission periods between transmitted bits, reads all eight data bits received at the receive terminal from the received bit. Thereafter, the microprocessor re-enables the NMI enable switch and resumes the suspended on-going processes. In a transmit mode, the microprocessor writes a binary 1, corresponding to a start bit, to the transmit bit, causing a transmit signal to be output from the transmit terminal. The microprocessor then transmits the eight bits corresponding to the desired transmit byte, each bit being separated by the appropriate inter-bit serial communication time interval.

摘要翻译： 串行端口，其将串行传输的起始位传送到微处理器的不可屏蔽中断端，以确定微处理器响应于串行通信。 串行端口包括连接到串行端口的发送端的微处理器可读发送位，连接到串行端口的接收端的微处理器可读接收位和连接在接收端和NMI引脚之间的NMI使能开关 的微处理器。 在接收模式下，初始处于导通状态的NMI使能开关将串行传输的起始位直接发送到微处理器的NMI引脚，使微处理器中断正在进行的过程。 微处理器禁用NMI使能寄存器，并且在等待发送位之间的串行传输周期之后，从接收位读取在接收端接收的所有8个数据位。 此后，微处理器重新启用NMI启用开关并恢复暂停的正在进行的过程。 在发送模式中，微处理器将对应于起始位的二进制1写入发送位，使发送信号从发送终端输出。 然后，微处理器发送与期望的发送字节相对应的八个位，每个位被适当的位间串行通信时间间隔分隔开。

公开(公告)号：US5550997A

公开(公告)日：1996-08-27

申请号：US978491

申请日：1992-11-18

申请人： Tony K. Ip ,  Walter D. Kuver

发明人： Tony K. Ip ,  Walter D. Kuver

IPC分类号： G06F12/16 ,  G06F12/14 ,  G06F13/00 ,  G11C16/10

CPC分类号： G06F12/1433 ,  G11C16/102 ,  G06F2212/2022

摘要： Method and apparatus for loading a ROM image into PROM comprises loading a ROM image into a dynamic random access memory, verifying the accuracy of the ROM image in the dynamic random access memory, and receiving a command to flash EPROM with the stored ROM image. A hardware interlock mechanism is deactivated by a two-step command procedure so as to enable flashing the EPROM. Specifically, a predetermined bit pattern is written to a first predetermined address on an address bus, one bit being latched to cause a flash signal to be output to a transistor switch and to be pre-loaded at a flip flop. A second predetermined address is read from so as to clock the flip flop. The output of the flip flop closes the transistor switch allowing the flash enable signal to reach the EPROM. The EPROM is erased, after which the ROM image is loaded into the PROM.

摘要翻译： 将ROM图像加载到PROM中的方法和装置包括将ROM图像加载到动态随机存取存储器中，验证动态随机存取存储器中的ROM图像的精度，以及接收用存储的ROM图像闪存EPROM的命令。 通过两步命令程序禁用硬件互锁机制，以使EPROM闪烁。 具体地，将预定位模式写入地址总线上的第一预定地址，一位被锁存以使闪光信号输出到晶体管开关并在触发器中预加载。 读取第二预定地址以便对触发器进行时钟。 触发器的输出闭合晶体管开关，允许闪光使能信号到达EPROM。 擦除EPROM，然后将ROM映像加载到PROM中。

公开(公告)号：US5511151A

公开(公告)日：1996-04-23

申请号：US896367

申请日：1992-06-10

申请人： William C. Russell ,  H. Brad Emerson ,  Tony K. Ip

发明人： William C. Russell ,  H. Brad Emerson ,  Tony K. Ip

IPC分类号： B41J5/30 ,  B41J21/00 ,  G06K15/10 ,  G06T3/60 ,  H04N1/387 ,  H04N7/01

CPC分类号： G06K15/10 ,  G06K2215/0014 ,  G06K2215/0077

摘要： Method and apparatus for converting image data from row format into column format and a printer incorporating the same. A conversion circuit, which is responsive to writes to a first address space, is provided for converting the image data from the row format into the column format. A CPU writes the row format image data to the first address space whereupon the conversion circuit converts it to the second format. The CPU then writes image data to a second address space. In accordance with an unwind flag set by the CPU, either the converted image data or the original image data is stored in a memory. After the data has been written to memory, the CPU initiates a DMA transfer of the image data to a printer engine.

摘要翻译： 将图像数据从行格式转换为列格式的方法和装置以及包含该格式的打印机。 提供响应于对第一地址空间的写入的转换电路，用于将来自行格式的图像数据转换为列格式。 CPU将行格式图像数据写入第一地址空间，因此转换电路将其转换为第二格式。 CPU然后将图像数据写入第二个地址空间。 根据由CPU设置的展开标志，转换的图像数据或原始图像数据被存储在存储器中。 在将数据写入存储器之后，CPU启动图像数据的DMA传输到打印机引擎。

公开(公告)号：US6018787A

公开(公告)日：2000-01-25

申请号：US2382

申请日：1998-01-02

申请人： Tony K. Ip

发明人： Tony K. Ip

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/063 ,  G06F12/0653

摘要： A chip selection enable apparatus which outputs one of plural chip enable signals in correspondence to which of plural address signals appear on an address bus. The chip selection apparatus includes a programmable array logic device, connectable to the address bus, which is programmed to output at least one chip enable signal in response to address signals on the address bus, and which is also programmed to output N (N>1) coded signals in response to other address signals on the address bus. A decoder is connected to the programmable array logic device and decodes the N coded signals into at least N+1 chip enable signals. In one preferred embodiment, the programmable array logic device is configured to output five chip enable signals and three coded signals. A standard one-of-eight binary decoder decodes the three coded signals into eight additional chip enable signals, thereby providing 13 chip enable signals from a single programmable array logic device, even though the programmable array logic device is capable of outputting only eight outputs.

摘要翻译： 输出与多个地址信号中的哪一个相对应的多个芯片使能信号中的一个出现在地址总线上的芯片选择使能装置。 芯片选择装置包括可编程阵列逻辑器件，其可连接到地址总线，该可编程阵列逻辑器件被编程为响应于地址总线上的地址信号输出至少一个芯片使能信号，并且还编程为输出N（N> 1） ）编码信号，以响应地址总线上的其他地址信号。 解码器连接到可编程阵列逻辑器件，并将N个编码信号解码为至少N + 1个芯片使能信号。 在一个优选实施例中，可编程阵列逻辑器件被配置为输出五个芯片使能信号和三个编码信号。 八分之一二进制解码器将三个编码信号解码为八个附加芯片使能信号，从而提供来自单个可编程阵列逻辑器件的13个芯片使能信号，即使可编程阵列逻辑器件只能输出八个输出。

公开(公告)号：US5600804A

公开(公告)日：1997-02-04

申请号：US409035

申请日：1995-03-23

申请人： Tony K. Ip

发明人： Tony K. Ip

IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F13/16

CPC分类号： G06F13/1673

摘要： Apparatus for providing shared access to a shared RAM in situations where the shared RAM is electrically connected to a relatively slow address/data bus, and shared access is desired from a relatively faster address bus and data bus. An address buffer is connected between the address bus and the address/data bus, the address buffer for selectably buffering address information between those buses under control of an address buffer selection signal. A data buffer is connected between the data bus and the address/data bus, the data buffer for selectably buffering data information between those buses under control of a data buffer selection signal. A gate array is connected to the address/data bus, the gate array controlling access the shared RAM. A logic array is connected to the address bus and is responsive to address information on the address bus which corresponds to addresses of the shared RAM. In response to those addresses, the logic array activates the address buffer selection signal so as to cause the address buffer to buffer address information from the address bus onto the address/data bus, and thereafter by deactivating the address buffer selection signal and activating the data buffer selection signal so as to cause the data buffer to buffer data information from or to the address/data bus.

摘要翻译： 在共享RAM电连接到相对较慢的地址/数据总线和共享存取的情况下，从相对较快的地址总线和数据总线来看，期望提供对共享RAM的共享访问的装置。 地址缓冲器连接在地址总线和地址/数据总线之间，地址缓冲器用于在地址缓冲器选择信号的控制下可选地缓冲这些总线之间的地址信息。 数据缓冲器连接在数据总线和地址/数据总线之间，数据缓冲器用于在数据缓冲器选择信号的控制下可选地缓冲这些总线之间的数据信息。 门阵列连接到地址/数据总线，门阵列控制访问共享RAM。 逻辑阵列连接到地址总线，并响应地址总线上对应于共享RAM的地址的地址信息。 响应于这些地址，逻辑阵列激活地址缓冲器选择信号，使得地址缓冲器将地址总线上的地址信息缓存到地址/数据总线上，之后通过停止地址缓冲器选择信号并激活数据 缓冲器选择信号，以使数据缓冲器从地址/数据总线缓冲数据信息。