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公开(公告)号：US4326134A
公开(公告)日：1982-04-20
申请号：US71498
申请日：1979-08-31
IPC分类号： G11C5/14 , G11C11/34 , G11C16/06 , G11C16/30 , G11C17/00 , H01L27/02 , H02M7/25 , H02M9/06 , H03K4/02 , H03K5/02 , H03K5/12 , H03K3/57
CPC分类号： G11C16/30 , G11C5/145 , H01L27/0214 , H01L27/0218 , H03K4/02
摘要： Integrated circuit system for generating a rise-time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks. The maximum output voltage may be controlled by a gated diode reference device, which provides a reference voltage independent of power supply voltage. A feedback circuit may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level.
摘要翻译： 集成电路系统，用于利用由电容耦合的低电压时钟驱动的多个二极管连接级产生上升时间调节和电平控制的高电压脉冲。 最大输出电压可以由门控二极管参考器件控制，该器件提供与电源电压无关的参考电压。 可以提供反馈电路，其通过调制驱动高电压发生器的有效低电压时钟振幅来控制高电压上升时间。 还可以提供MOS逻辑电平接口电路用于感测达到预定的高电压电平。
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公开(公告)号：US4393481A
公开(公告)日：1983-07-12
申请号：US209131
申请日：1980-11-21
CPC分类号： G11C16/30 , G11C14/00 , G11C5/145 , H01L27/0218 , H03K4/02
摘要： Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.
摘要翻译： 采用集成浮栅电路元件的非易失性集成金属氧化物半导体随机存取存储器系统，以及用于在提供独立的，非易失性的电气可变静态RAM电路系统中产生和控制高电压的集成装置。
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公开(公告)号：US4263664A
公开(公告)日：1981-04-21
申请号：US71499
申请日：1979-08-31
CPC分类号： G11C5/145 , G11C14/00 , H01L27/0214 , H01L27/0218 , H03K4/02
摘要： Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.
摘要翻译： 采用集成浮栅电路元件的非易失性集成金属氧化物半导体随机存取存储器系统，以及用于在提供独立的，非易失性的电气可变静态RAM电路系统中产生和控制高电压的集成装置。
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公开(公告)号：US4007446A
公开(公告)日：1977-02-08
申请号：US592156
申请日：1975-06-30
CPC分类号： G11C19/287
摘要： The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two-phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit. The input and output sections each contain the same number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site. Data bits are transferred from the input section to the central section in two phases. Data bits are also transferred from the central section to the output section in two phases. This interleaved mode of inter-sectional data transfer allows for input and output sections of a minimum size (in terms of number of cell sites required) and hence, a greater density CCD register. The interleaved mode also reduces the number of charge transfer from input to output, thereby providing inherent charge transfer efficiency.
摘要翻译： 本发明包括一个电荷耦合器件移位寄存器，用于存储和传送小数据包形式的信息位。 该装置利用多相时钟，允许寄存器内的高密度存储，由三部分组成：串行输入部分，中央存储部分和串行输出部分。 串行输入部分从注射器电路同步接收电荷分组并由两相时钟驱动。 中心部分形成存储和传送机制的核心，并由多相时钟驱动。 串行输出部分也由两相时钟驱动，同步发射由读出放大器电路检测和放大的电荷分组。 输入和输出部分每个包含与通过中心部分并行传送的位数相同的单元格位置数。 然而，这些部分仅在每个其他小区站点中存储数据位。 数据位分两个阶段从输入部分转移到中央部分。 数据位也分两个阶段从中央部分传输到输出部分。 这种分段数据传输的交错模式允许具有最小尺寸（就所需的单元位置的数量）而言的输入和输出部分，因此更大密度的CCD寄存器。 交错模式还减少了从输入到输出的电荷转移的数量，从而提供固有的电荷转移效率。
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5.发明授权Multiphase series-parallel-series charge-coupled device registers with simplified input clocking 失效多相串并联串联电荷耦合器件寄存器，具有简化的输入时钟
公开(公告)号：US4024514A
公开(公告)日：1977-05-17
申请号：US591724
申请日：1975-06-30
CPC分类号： G11C19/287
摘要： The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit.The input and output sections each contain (almost) twice the number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site. Data bits are transferred into and out of the central section in one parallel step, thereby minimizing the clocking requirements of the register and allowing for high density CCD chips containing such registers.
摘要翻译： 本发明包括一个电荷耦合器件移位寄存器，用于存储和传送小数据包形式的信息位。 该装置利用多相时钟，允许寄存器内的高密度存储，由三部分组成：串行输入部分，中央存储部分和串行输出部分。 串行输入部分从注射器电路同步接收电荷分组并由两相时钟驱动。 中心部分形成存储和传送机制的核心，并由多相时钟驱动。 串行输出部分也由两相时钟驱动，同步发射由读出放大器电路检测和放大的电荷分组。
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公开(公告)号：US4021682A
公开(公告)日：1977-05-03
申请号：US591667
申请日：1975-06-30
申请人： Ben R. Elmer , Wallace E. Tchon
发明人： Ben R. Elmer , Wallace E. Tchon
IPC分类号： G11C27/04 , G11C19/28 , H01L21/339 , H01L29/762 , H03K5/20 , H03K3/353 , H03K5/18
CPC分类号： G11C19/287 , G11C19/285
摘要： The invention comprises circuitry for detecting relatively small amounts of charge emitted from a CCD register. The circuit acts as a differential amplifier, differentiating between charge levels corresponding to logical zeros and logical ones and generates corresponding system level logic signals. A reference charge is developed by a self-tracking reference charge injector. Both the reference charge and the charge packet to be sensed are coupled to the differential amplifier via buffering diode-coupled transistors. The circuit provides for a REFRESH mode of operation, but may be modified to also allow for READ, WRITE or PARTIAL-WRITE modes of operation.
摘要翻译： 本发明包括用于检测从CCD寄存器发射的相对少量电荷的电路。 该电路用作差分放大器，区分对应于逻辑0和逻辑0的电荷电平，并产生相应的系统电平逻辑信号。 参考电荷由自动跟踪参考电荷注入器开发。 参考电荷和要感测的电荷分组都通过缓冲二极管耦合的晶体管耦合到差分放大器。 该电路提供了REFRESH操作模式，但可以修改为也允许读取，写入或部分写入操作模式。
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公开(公告)号：US3986179A
公开(公告)日：1976-10-12
申请号：US591666
申请日：1975-06-30
申请人： Ben R. Elmer , Wallace E. Tchon
发明人： Ben R. Elmer , Wallace E. Tchon
CPC分类号： G11C29/86 , G06F12/0676 , G11C19/287
摘要： The invention comprises a CCD memory chip. A CCD chip is comprised of a plurality of arrays, each of which is in turn comprised of a plurality of CCD registers. A serial addressing system may be used to determine which of the arrays is accessed. Fault-tolerance with respect to defective arrays is achieved by the combination of having only the address circuits for properly functioning arrays form the bits of an N-bit addressing shift register, (whereas the address circuits for improperly functioning arrays are shorted such that they do not form a bit of the N-bit address shift register,) and disabling the voltage delivered to a faulty array. The control circuitry includes the address circuitry and further includes means for controllably providing power to the array components. A plurality of arrays comprises a chip having pads for connecting the chip to the rest of the system.
摘要翻译： 本发明包括一个CCD存储芯片。 CCD芯片由多个阵列组成，每个阵列又由多个CCD寄存器组成。 可以使用串行寻址系统来确定哪些阵列被访问。 通过组合只有适当正常工作的阵列的地址电路形成N位寻址移位寄存器的位来实现，而不正确运行的阵列的地址电路短路，这样它们就可以实现 不构成N位地址移位寄存器的一部分），并禁用传送到故障阵列的电压。 控制电路包括地址电路，并且还包括用于可控地向阵列组件提供电力的装置。 多个阵列包括具有用于将芯片连接到系统的其余部分的垫的芯片。
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公开(公告)号：US3986172A
公开(公告)日：1976-10-12
申请号：US591723
申请日：1975-06-30
申请人： Ben R. Elmer , Wallace E. Tchon
发明人： Ben R. Elmer , Wallace E. Tchon
CPC分类号： G11C19/287 , G11C19/285
摘要： Interface circuitry for a charged coupled device (CCD) register system. The circuitry enables a PARTIAL-WRITE mode of operation on a CCD storage register. A data bus, which may be bi-directional, is coupled to the sense amplifier of the CCD storage register. The coupling is via interface circuitry responsive to control signals for enabling the register and also enabling a WRITE operation. Discontinuation of the WRITE signals frees the data bus for other uses, thereby allowing for a PARTIAL-WRITE mode of operation. The interface circuitry is simplified so as to require a minimum of space, thereby enhancing the density characteristics of the CCD storage system.
摘要翻译： 用于充电耦合器件（CCD）寄存器系统的接口电路。 该电路实现CCD存储寄存器上的部分写操作模式。 可以是双向的数据总线耦合到CCD存储寄存器的读出放大器。 耦合是通过接口电路来响应控制信号以启用寄存器，并且还使能写入操作。 WRITE信号的停止将数据总线释放出来用于其他用途，从而允许采用部分写操作模式。 接口电路被简化为要求最小的空间，从而增强了CCD存储系统的密度特性。
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公开(公告)号：US3980902A
公开(公告)日：1976-09-14
申请号：US592147
申请日：1975-06-30
申请人： Wallace E. Tchon
发明人： Wallace E. Tchon
IPC分类号： G11C19/28 , G11C27/04 , H01L21/339 , H01L29/762 , H01L29/768 , H03K3/353 , H01L29/78
CPC分类号： G11C27/04 , G11C19/287 , H01L29/76808
摘要： A device for injecting precisely controlled amounts of charge corresponding to data bits, into charge-coupled device registers. The device converts input signals in the form of logic level voltages into relatively small packets of charge. The device allows for relatively large variations at its input terminal, yet still produces highly controlled levels of charge at its output terminal. The output level of charge is also highly controlled despite variations in process parameters for a semiconductor wafer.
摘要翻译： 用于将与数据位对应的精确控制量的电荷注入到电荷耦合器件寄存器中的器件。 该装置将逻辑电平电压形式的输入信号转换成相对较小的电荷分组。 该器件在其输入端子允许相对较大的变化，但仍然在其输出端子处产生高度受控的电荷电平。 即使半导体晶片的工艺参数有变化，电荷的输出电平也受到高度的控制。
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