利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.021 秒)

    Integrated rise-time regulated voltage generator systems
    2.
    发明授权
    Integrated rise-time regulated voltage generator systems 失效
    集成上升时间调节电压发生器系统

    公开(公告)号：US4326134A

    公开(公告)日：1982-04-20

    申请号：US71498

    申请日：1979-08-31

    申请人： William H. Owen ,  Richard T. Simko ,  Wallace E. Tchon

    发明人： William H. Owen ,  Richard T. Simko ,  Wallace E. Tchon

    IPC分类号： G11C5/14 ,  G11C11/34 ,  G11C16/06 ,  G11C16/30 ,  G11C17/00 ,  H01L27/02 ,  H02M7/25 ,  H02M9/06 ,  H03K4/02 ,  H03K5/02 ,  H03K5/12 ,  H03K3/57

    CPC分类号： G11C16/30 ,  G11C5/145 ,  H01L27/0214 ,  H01L27/0218 ,  H03K4/02

    摘要： Integrated circuit system for generating a rise-time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks. The maximum output voltage may be controlled by a gated diode reference device, which provides a reference voltage independent of power supply voltage. A feedback circuit may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level.

    摘要翻译： 集成电路系统，用于利用由电容耦合的低电压时钟驱动的多个二极管连接级产生上升时间调节和电平控制的高电压脉冲。 最大输出电压可以由门控二极管参考器件控制，该器件提供与电源电压无关的参考电压。 可以提供反馈电路，其通过调制驱动高电压发生器的有效低电压时钟振幅来控制高电压上升时间。 还可以提供MOS逻辑电平接口电路用于感测达到预定的高电压电平。

    Integrated circuit high voltage pulse generator system
    4.
    发明授权
    Integrated circuit high voltage pulse generator system 失效
    集成电路高压脉冲发生器系统

    公开(公告)号：US4404475A

    公开(公告)日：1983-09-13

    申请号：US252231

    申请日：1981-04-08

    申请人： Joseph Drori ,  William H. Owen, III ,  Richard T. Simko

    发明人： Joseph Drori ,  William H. Owen, III ,  Richard T. Simko

    IPC分类号： G11C5/14 ,  G11C11/34 ,  G11C16/30 ,  H03K3/45 ,  H03K3/01 ,  H03L5/00

    CPC分类号： G11C5/145 ,  G11C11/34 ,  G11C16/30

    摘要： An integrated circuit system for generating a regulated high voltage tunneling pulse whose voltage level varies as a function of the voltage level needed to initiate tunneling of electrons across one or more dielectric gaps between respective first and second regions. The voltage level of initial electron tunneling is compared with a predetermined voltage margin so as to cause said generated tunneling voltage pulse to have a voltage level equal to the sum of said detected tunneling voltage and said voltage margin. The tunneling voltage pulse is then maintained substantially at this level for a predetermined duration before the tunneling pulse is discharged.

    摘要翻译： 一种用于产生调节的高电压隧道脉冲的集成电路系统，其电压电平随着电子穿过相应的第一和第二区域之间的一个或多个电介质间隙而引起的电压所需的电压电平变化。 将初始电子隧穿的电压电平与预定的电压余量进行比较，以使所述产生的隧穿电压脉冲的电压电平等于所检测的隧穿电压和所述电压余量之和。 然后在隧道脉冲放电之前，将隧道电压脉冲基本保持在该电平预定的持续时间。

    Clocked high voltage switch
    6.
    发明授权
    Clocked high voltage switch 失效
    时钟高压开关

    公开(公告)号：US5723985A

    公开(公告)日：1998-03-03

    申请号：US590267

    申请日：1995-11-21

    申请人： Hieu Van Tran ,  Trevor Blyth ,  Richard T. Simko

    发明人： Hieu Van Tran ,  Trevor Blyth ,  Richard T. Simko

    IPC分类号： H03K19/0185 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H03K17/10 ,  H03K19/0175

    CPC分类号： H03K17/102 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/4238 ,  H01L29/78

    摘要： The present invention discloses methods and apparatus for implementing a clocked high voltage switch involving MOS devices. The switching is from a high voltage source typically at 21V to ground. An intermediate voltage source typically at 11V is introduced for reducing the gated breakdown voltage requirement to approximately 10V. This reduced gated breakdown voltage requirement is easily met by special layout methods applied to various transistors in the circuit. The basic layout methods include the terminating of the field implant region near the N+P junction to expose the N+ diffusion over the P substrate to increase the junction breakdown and the gated diode breakdown, and the use of short channel length to reduce the threshold voltage.

    摘要翻译： 本发明公开了用于实现涉及MOS器件的时钟高压开关的方法和装置。 开关电源通常为21V至高压电源。 引入通常为11V的中间电压源，以将门控击穿电压要求降低到约10V。 这种降低的门控击穿电压要求通过应用于电路中的各种晶体管的特殊布局方法容易地满足。 基本布局方法包括在N + P结附近终止场注入区，以暴露P衬底上的N +扩散，以增加结击穿和门控二极管击穿，以及使用短沟道长度来降低阈值电压 。

    Triple layer polysilicon cell
    8.
    发明授权
    Triple layer polysilicon cell 失效
    三层多晶硅电池

    公开(公告)号：US4099196A

    公开(公告)日：1978-07-04

    申请号：US810912

    申请日：1977-06-29

    申请人： Richard T. Simko

    发明人： Richard T. Simko

    IPC分类号： G11C16/04 ,  H01L29/788

    CPC分类号： G11C16/0425 ,  H01L29/7883

    摘要： A triple layer polysilicon cell for use in an electrically erasable PROM or for a discretionary circuit connector is described. Tunneling is employed to transfer charge to a floating gate from a programming gate and also to transfer charge from the floating gate to an erasing gate. Through light doping steps, the first layer of polysilicon (programming gate) and a second layer of polysilicon (floating gate) include rough surfaces. These rough surfaces provide enhanced electric fields which allow tunneling through relatively thick oxides.

    摘要翻译： 描述了用于电可擦除PROM或任意电路连接器的三层多晶硅单元。 采用隧道技术将电荷从编程门传输到浮动栅极，并将电荷从浮动栅极传输到擦除栅极。 通过轻掺杂步骤，第一层多晶硅（编程门）和第二层多晶硅（浮栅）包括粗糙表面。 这些粗糙的表面提供增强的电场，其允许通过相对较厚的氧化物穿透。

    Non-volatile electrically alterable semiconductor memory for analog and digital storage
    9.
    发明授权
    Non-volatile electrically alterable semiconductor memory for analog and digital storage 失效
    用于模拟和数字存储的非易失性电可变半导体存储器

    公开(公告)号：US5973956A

    公开(公告)日：1999-10-26

    申请号：US509348

    申请日：1995-07-31

    申请人： Trevor Blyth ,  Richard T. Simko

    发明人： Trevor Blyth ,  Richard T. Simko

    IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C27/00 ,  G11C7/00

    CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C27/005 ,  G11C7/16

    摘要： Methods and apparatus for achieving analog storage in a non-volatile memory array. The array consists of memory cells that utilize Fowler-Nordheim tunneling for erasure and hot electron injection for programming. Writing into a cell is performed by an initial erasure followed by a controlled sequence of program operations during which the cell is programmed in small increments. The stored voltage is read after each program step and when the voltage read back from the cell is equal or just beyond the desired analog level, the sequence of program steps is terminated. The read condition for the cell applies a positive voltage to the drain or common line and a positive voltage to the control gate. The source is connected through a load device to a negative (ground) supply. The output from the cell is the actual voltage that exists at the source node. There is no current sensing or comparison with a reference voltage to determine the output state. A digital number can be represented by assigning a specific analog level to a digital number. The range of digital numbers that can be represented is determined by the analog voltage range divided by the accuracy to which the voltage may be stored and reliably retrieved. Other aspects and features of the invention are disclosed.

    摘要翻译： 用于在非易失性存储器阵列中实现模拟存储的方法和装置。 该阵列由使用Fowler-Nordheim隧道擦除和热电子注入进行编程的存储器单元组成。 通过初始擦除执行写入单元格，随后是程序操作的受控序列，在该程序操作期间以小的增量对单元进行编程。 在每个程序步骤之后读取存储的电压，并且当从单元读回的电压相等或刚好超过所需的模拟电平时，程序步骤的顺序终止。 单元的读取条件将正电压施加到漏极或公共线，并向控制栅施加正电压。 源通过负载设备连接到负（地）电源。 单元格的输出是存在于源节点的实际电压。 没有电流检测或与参考电压进行比较以确定输出状态。 可以通过将特定模拟电平分配给数字号码来表示数字号码。 可以表示的数字数字的范围由模拟电压范围除以电压可以被存储和可靠地检索的精度决定。 公开了本发明的其它方面和特征。

    Single-transistor cell EEPROM array for analog or digital storage
    10.
    发明授权
    Single-transistor cell EEPROM array for analog or digital storage 失效
    用于模拟或数字存储的单晶体管单元EEPROM阵列

    公开(公告)号：US5294819A

    公开(公告)日：1994-03-15

    申请号：US981610

    申请日：1992-11-25

    申请人： Richard T. Simko

    发明人： Richard T. Simko

    IPC分类号： G11C16/04 ,  G11C27/00 ,  H01L27/115 ,  H01L29/788 ,  H01L29/78

    CPC分类号： G11C16/0416 ,  G11C27/005 ,  H01L27/115 ,  H01L29/7883

    摘要： The present invention discloses methods and apparatus for implementing a single-transistor cell EEPROM array for analog or digital storage. The single-transistor storage cell is made possible by continuously maintaining a net negative charge on the floating gate of the EEPROM storage transistor. Furthermore, according to the present invention, a dense layout of the single-transistor cells is possible by sharing a common diffusion region between the transistors located in the same row and the transistors located in one adjacent row. This common diffusion region functions as a source in the erase and program modes, and as a drain in the read mode. Moreover, the common diffusion feature of the present invention allows the use of a single level of metal in distributing the various operating voltages to the EEPROM storage transistors. Further, utilizing a single level of metal allows for a simple and dense fabrication and also reduces the parasitic capacitances in the EEPROM storage array. Array operating voltages are chosen such that "program disturbance" is eliminated on cells adjacent to a cell undergoing programming. Finally, the present invention utilizes only a single polarity of operating voltages.

    摘要翻译： 本发明公开了用于实现用于模拟或数字存储的单晶体管单元EEPROM阵列的方法和装置。 单晶体管存储单元可以通过在EEPROM存储晶体管的浮动栅极上连续地保持净负电荷来实现。 此外，根据本发明，通过在位于同一行的晶体管和位于相邻行中的晶体管之间共享公共扩散区，可以实现单晶体管单元的致密布局。 该公共扩散区域在擦除和编程模式中用作源，并在读取模式下用作漏极。 此外，本发明的共同扩散特征允许使用单个级别的金属将各种工作电压分配给EEPROM存储晶体管。 此外，利用单层金属允许简单且致密的制造，并且还减少了EEPROM存储阵列中的寄生电容。 选择阵列工作电压，使得在正在进行编程的单元相邻的单元上消除“程序干扰”。 最后，本发明仅使用单个极性的工作电压。