公开(公告)号：US20180366197A1

公开(公告)日：2018-12-20

申请号：US15997717

申请日：2018-06-05

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Shao-Ching Liao ,  Ming-Che Lin ,  Min-Chih Wei ,  Chuan-Sheng Chou

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147

Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.

公开(公告)号：US10475513B2

公开(公告)日：2019-11-12

申请号：US15997717

申请日：2018-06-05

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Shao-Ching Liao ,  Ming-Che Lin ,  Min-Chih Wei ,  Chuan-Sheng Chou

IPC: G11C13/00 ,  H01L45/00

Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.

公开(公告)号：US20180374558A1

公开(公告)日：2018-12-27

申请号：US15683733

申请日：2017-08-22

Applicant: Winbond Electronics Corp.

Inventor： Chuan-Sheng Chou ,  Meng-Hung Lin ,  Bo-Lun Wu ,  Chia-Hua Ho

IPC: G11C29/50

Abstract: A memory storage apparatus including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory cells. The memory cell array is configured to store data. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to apply one of a set signal and a reset signal to a target memory cell among the memory cells to generate a read current. The memory control circuit receives a read current of the target memory cell. The memory control circuit compares the read current with a reference current. The memory control circuit determines whether the target memory cell is failed according to a comparison result. In addition, a method for testing a memory storage apparatus is also provided.

公开(公告)号：US09443587B1

公开(公告)日：2016-09-13

申请号：US14804354

申请日：2015-07-21

Applicant: Winbond Electronics Corp.

Inventor： Frederick Chen ,  Meng-Hung Lin ,  Ping-Kun Wang ,  Shao-Ching Liao ,  Chuan-Sheng Chou

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.

Abstract translation: 提供了一种电阻式存储装置及其写入方法。 在该方法中，接收逻辑数据，并且选择相应的电阻性存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平（其中对应的电阻性存储单元的第一读取电流大于第一参考电流）时，在写入周期期间将设置脉冲和复位脉冲提供给电阻存储器单元。 当逻辑数据处于第二逻辑电平时，其中电阻存储单元的第二读取电流小于第二参考电流，在写入周期期间将复位脉冲提供给电阻存储单元。 复位脉冲和设定脉冲的极性相反。